Method and apparatus for application's specific testing of assembled circuits

• US 6,038,520 A
• Filed: 10/02/1998
• Issued: 03/14/2000
• Est. Priority Date: 10/02/1998
• Status: Expired due to Term

• Current Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Lau, Lee, Ho, Sam, Man, Albert, Schoonover, Roy
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Bui, Bryan
• Application Number:
  US09/166,207
• Time in Patent Office: 529 Days
• Field of Search: 702/117, 702/118, 702/119, 702/120, 702/121, 702/108, 702/123, 702/122, 324/73.1, 714/740, 714/741, 714/742
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31903 tester configuration

Abstract

A method and apparatus for testing specific assembled circuits begins by configuring a plurality of applications specific testing entities to test assembled circuits, where the configuring is based on the types of assembled circuits being tested. Next, a specific assembled circuit testing program is provided to the corresponding application specific testing entity based on the type of assembled circuits it is testing. In addition to providing the testing programs to the testing entities, programming instructions are provided to a programmable handler to pick and place the appropriate assembled circuits with the corresponding applications specific testing entities. When the testing of a particular assembled circuit is complete, a test complete indication is provided. When the test complete indication is received by the host, programming instructions are provided to the programmable handler to remove the integrated circuit from the testing entity and place another integrated circuit in the proximity of the testing entity for subsequent testing.

Claims

1. An application specific testing system comprises:

a plurality of application specific testing entities, wherein each of the plurality of application specific testing entities is programmable to test at least one of a plurality of assembled circuits;

a programmable handler operable to pick and place assembled circuits of the plurality of assembled circuits in proximity of corresponding ones of the plurality of application specific testing entities such that placed assembled circuits are subject to testing; and

a host processing entity operably coupled to the plurality of application specific testing entities and the programmable handler, wherein the host processing entity administers picking and placing by the programmable handler and testing by the plurality of application specific testing entities.

2. The application specific testing system of claim 1, wherein an application specific testing entity of the plurality of application specific testing entities further comprises a computer structure lacking a corresponding component of the one of the plurality of assembled circuits, wherein, when the one of the plurality of assembled circuits is being tested by the application specific testing entity, a combination of the one of the plurality of assembled circuits and the application specific testing entity forms a specific functional computer.

3. The application specific testing system of claim 1, wherein the plurality of assembled circuits further comprises at least one type of:

assembled printed circuit boards, integrated circuits, Application Specific Integrated Circuits, and a wafer of integrated circuit die.

4. The application specific testing system of claim 1, wherein the host processing entity further comprises a plurality of testing programs and specific testing system operation controlling instructions that cause at least some of the plurality of application specific testing entities to test different types of the plurality of assembled circuits in a time contemporaneous manner.

5. The application specific testing system of claim 1, wherein the host processing entity further comprises operational controlling instructions that cause the plurality of application specific testing entities to provide testing data to the host processing entity, wherein the host processing entity compiles the testing data into test result categories.

6. The application specific testing system of claim 1, wherein the host processing entity further comprises a plurality of specific assembled circuit testing programs, and wherein the host processing entity provides at least one of the plurality of specific assembled circuit testing programs to at least one of the plurality of application specific testing entities based on the at least one of the plurality of assembled circuits under test.

7. The application specific testing system of claim 6, wherein at least one of the plurality of specific assembled circuit testing programs further comprises an analog circuit testing program that tests an analog portion of the at least one of the plurality of assembled circuits based on acceptance of an expected signature.

8. The application specific testing system of claim 1, wherein the host processing entity further comprises operational controlling instructions that cause the host processing entity to monitor testing by the plurality of application specific testing entities, and wherein, when one of the plurality of application specific testing entities overruns a test time period, the host processing entity reboots the one of the plurality of application specific testing entities.

9. A method for testing assembled circuits, the method comprises the steps of:

a) configuring a plurality of application specific testing entities to test the assembled circuits based on types of the assembled circuits to be tested;

b) providing a specific assembled circuit testing program to a corresponding one of the plurality of application specific testing entities based on the type of assembled circuits being tested by the corresponding one of the plurality of application specific testing entities;

c) providing programming instructions to a programmable handler to pick and place at least one of the assembled circuits in proximity of the corresponding one of the plurality of application specific testing entities to produce a placed assembled circuit;

d) receiving a test complete indication by the host processing entity when testing of the placed assembled circuit by the corresponding one of the plurality of application specific testing entities is to be complete; and

e) providing programming instructions to the programmable handler to remove the placed assembled circuit in one of a plurality of application specific testing entities and to pick and place at least another one of the assembled circuits to a corresponding application specific testing entity when the test complete indication hasbeen received.

10. The method of claim 9, wherein step (a) further comprises configuring the plurality of application specific testing entities by enabling the plurality of application specific testing entities to test a single type of assembled circuits.

11. The method of claim 9, wherein step (a) further comprises configuring the plurality of application specific testing entities by:

obtaining data regarding the assembled circuits to be tested, wherein the data includes type of assembled circuits and corresponding quantities;

configuring the plurality of application specific testing entities into groups based on the type of assembled circuits and the corresponding quantity.

12. The method of claim 9, wherein step (b) further comprises:

enabling one of a plurality of specific assembled circuit testing programs stored in the corresponding one of the plurality of application specific testing entities based on the type of assembled circuit being tested.

13. The method of claim 9, wherein step (b) further comprises:

providing one of a plurality of specific assembled circuit testing programs stored in a host processing entity to the corresponding one of the plurality of application specific testing entities based on the type of assembled circuit being tested.

14. The method of claim 9, wherein the test complete indications further comprises at least one of:

test results, a test end flag, and an expiration of a test time period.

15. The method of claim 14 further comprises compiling the test results into categories of at least level of test passes and types of test failures.

16. The method of claim 9 further comprises:

receiving a placing indication by the host processing entity from the programmable handler, wherein the placing indication indicates that the placed assembled circuit is placed;

enabling the corresponding one of the plurality of application specific testing entities to commence testing when the placing indication is received by the host processing entity, wherein the enabling includes applying power to the assembled circuit and testing the assembled circuit based on the specific assembled circuit testing program; and

disabling the corresponding one of the plurality of application specific testing entities when the test complete indication is received by the host processing entity, wherein the disabling includes removing power from the assembled circuit.

17. A method for testing assembled circuits, the method comprises the steps of:

a) obtaining data regarding the assembled circuits to be tested, wherein the data includes at least one of;

type of assembled circuits and quantities of the assembled circuits by type;

b) providing a specific assembled circuit test program by a host processing entity to a configured one of a plurality of application specific testing entities based on the data;

c) providing pick-place-remove programming instructions by the host processing entity to a programmable handlers based on the data; and

d) controlling by the host processing entity testing by the configured one of the plurality of application specific testing entities and picking, placing, and removing of the assembled circuits by the programmable handler.

18. The method of claim 17, wherein step (a) further comprises obtaining the data from at least one of:

user interface, scan of identifying code of the assembled circuit, and package type.

19. The method of claim 17 further comprises:

providing another specific assembled circuit test program by the host processing entity to another configured one of the plurality of application specific testing entities based on the data; and

updating the pick-place-remove programing instructions such that the programmable handler provides a first type of assembled circuits to the configured one of the plurality of application specific testing entities and a second type of assembled circuits to the another configured one of the plurality of application specific testing entities.

20. The method of claim 17 further comprises compiling test results from the configured one of the plurality of application specific testing entities by the host processing entity.

21. The method of claim 17, wherein step (d) further comprises:

receiving a placing indication by the host processing entity from the programmable handler, wherein the placing indication indicates that the assembled circuit is placed;

enabling the configured one of the plurality of application specific testing entities by the host processing entity to commence testing of the assembled circuit when the placing indication is received, wherein the enabling includes applying power to the assembled circuit and testing the assembled circuit based on the specific assembled circuit testing program; and

disabling the configured one of the plurality of application specific testing entities by the host processing entity when a test complete indication is received, wherein the disabling includes removing power form the assembled circuit.

22. A host processing entity for use in an application specific testing system, the host processing entity comprises:

a processing module; and

memory operably coupled to the processing module, wherein the memory includes operating instructions that cause the processing module to (a) configure a plurality of application specific testing entities to test the assembled circuits based on types of the assembled circuits to be tested;

(b) provide a specific assembled circuit testing program to a corresponding one of the plurality of application specific testing entities based on the type of assembled circuits being tested by the corresponding one of the plurality of application specific testing entities;

(c) provide programming instructions to a programmable handler to pick and place at least one of the assembled circuits in proximity of the corresponding one of the plurality of application specific testing entities to produce a placed assembled circuit;

(d) receive a test complete indication when testing of the placed assembled circuit by the corresponding one of the plurality of application specific testing entities is to be complete; and

(e) provide programming instructions to the programmable handler to removed the placed assembled circuit and to pick and place at least another one of the assembled circuits when the test complete indication has been received.

23. The host processing entity of claim 22, wherein the memory further comprises operating instructions that cause the processing module to configure the plurality of application specific testing entities by enabling the plurality of application specific testing entities to test a single type of assembled circuits.

24. The host processing entity of claim 22, wherein the memory further comprises operating instructions that cause the processing module to configure the plurality of application specific testing entities by:

obtaining data regarding the assembled circuits to be tested, wherein the data includes type of assembled circuits and corresponding quantities;

configuring the plurality of application specific testing entities into groups based on the type of assembled circuits and the corresponding quantity.

25. The host processing entity of claim 22, wherein the memory further comprises operating instructions that cause the processing module to:

enable one of a plurality of specific assembled circuit testing programs stored in the corresponding one of the plurality of application specific testing entities based on the type of assembled circuit being tested.

26. The host processing entity of claim 22, wherein the memory further comprises operating instructions that cause the processing module to:

provide one of a plurality of specific assembled circuit testing programs stored in a host processing entity to the corresponding one of the plurality of application specific testing entities based on the type of assembled circuit being tested.

27. The host processing entity of claim 22, wherein the memory further comprises operating instructions that cause the processing module to compile test results into categories of at least level of test passes and types of test failures.

28. The host processing entity of claim 22, wherein the memory further comprises operating instructions that cause the processing module to:

receive a placing indication from the programmable handler, wherein the placing indication indicates that the placed assembled circuit is placed;

enable the corresponding one of the plurality of application specific testing entities to commence testing when the placing indication is received, wherein the enabling includes applying power to the assembled circuit and testing the assembled circuit based on the specific assembled circuit testing program; and

disable the corresponding one of the plurality of application specific testing entities when the test complete indication is received, wherein the disabling includes removing power from the assembled circuit.

29. A host processing entity for use in an application specific testing system, the host processing entity comprises:

a processing module; and

memory operably coupled to the processing module, wherein the memory includes operating instructions that cause the processing module to (a) obtain data regarding the assembled circuits to be tested, wherein the data includes at least one of;

type of assembled circuits and quantities of the assembled circuits by type;

(b) provide a specific assembled circuit test program to a configured one of a plurality of application specific testing entities based on the data;

(c) provide pick-place-remove programming instructions to a programmable handlers based on the data; and

(d) control testing by the configured one of the plurality of application specific testing entities and picking, placing, and removing of the assembled circuits by the programmable handler.

30. The host processing entity of claim 29, wherein the memory further comprises operating instructions that cause the processing module to:

provide another specific assembled circuit test program to another configured one of the plurality of application specific testing entities based on the data; and

update the pick-place-remove programming instructions such that the programmable handler provides a first type of assembled circuits to the configured one of the plurality of application specific testing entities and a second type of assembled circuits to the another configured one of the plurality of application specific testing entities.

31. The host processing entity of claim 29, wherein the memory further comprises operating instructions that cause the processing module to compile test results from the configured one of the plurality of application specific testing entities.

32. The host processing entity of claim 29, wherein the memory further comprises operating instructions that cause the processing module to:

receive a placing indication from the programmable handler, wherein the placing indication indicates that the assembled circuit is placed;

enable the configured one of the plurality of application specific testing entities to commence testing of the assembled circuit when the placing indication is received, wherein the enabling includes applying power to the assembled circuit and testing the assembled circuit based on the specific assembled circuit testing program; and

disable the configured one of the plurality of application specific testing entities when a test complete indication is received, wherein the disabling includes removing power from the assembled circuit.