Bit-depth increase by bit replication

• US 6,038,576 A
• Filed: 12/02/1997
• Issued: 03/14/2000
• Est. Priority Date: 12/02/1997
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Ulichney, Robert A., Cheung, Shiufun
• Primary Examiner(s): NGO, CHUONG D
• Application Number:
  US08/982,954
• Time in Patent Office: 833 Days
• Field of Search: 708/200, 708/203, 708/204, 708/208, 708/209, 708/400, 341/95
• US Class Current: 708/208
• CPC Class Codes: G06F 5/00 Methods or arrangements for data conversion without changing the order or content of the data handled

Abstract

A method for bit-depth increasing digital data represented by a first number of original bits which are sequentially ordered beginning with a start bit and ending with an end bit. To bit-depth increase the data, in an expanded presentation, the original bits are replicated in the sequential order starting with the start bit to form replication bits. The original bits are appended with a second number of the replication bits to form the expanded presentation of the digital data. The appended replication bits start with the start bit and are in the sequential order of the original bits.

Claims

1. An apparatus for bit-depth increasing digital data, comprising:

an input shift register having a first number of registers configured to store original data bits;

an output shift register having a second number of registers, the second number being greater than the first number, configured to store the original data bits and replication data bits representing replicated original bits;

a first connector configured to connect the input shift register to the output shift register such that the original data bits are transmitted from the input shift register to the output shift register; and

a second connector configured to connect the first connector to the input shift register such that each of the original data bits transmitted to the output shift register is also transmitted back to the first shift register for storage in one of the first number of registers;

wherein the original data bits are sequentially transmitted from the first shift register to the second shift register via the first connector until each of the second number of registers stores one of an original data bit and a replication bit.

2. An apparatus according to claim 1, wherein:

the input shift register initially stores the original data bits in a sequential order starting with a most significant and ending with a least significant bit.

3. An apparatus according to claim 2, wherein:

the replication bits represent replicated original bits in the sequential order.

4. An apparatus according to claim 2, wherein:

the original bits are transmitted from the input shift register to the output shift register in the sequential order.

5. An apparatus according to claim 1, wherein:

the original data bits are stored in the sequential order as the most significant bits in the output shift register, and the replication bits replicate one or more of the original data bits and are stored in the sequential order as the least significant bits in the output shift register.

6. An apparatus according to claim 1, wherein:

the replication bits replicate at least one of the original data bits more than once.

7. An apparatus according to claim 1, wherein:

the replication bits replicate some of the original data bits more than other of the original data bits.