Synchronized MIMD multi-processing system and method of operation
First Claim
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1. A synchronization system comprising:
- a synchronization bus having a plurality of bus lines;
a plurality of processors, equal in number to the number of bus lines in said synchronization bus, each processor fetching and executing instructions independently of other processors, each processor includinga program counter register storing an address of a next instruction for fetching said next instruction;
a synchronization register having a plurality of bits equal in number to the number of processors, each bit corresponding to a unique one of said plurality of processors, said synchronization register having stored therein an indication of which if any other of said processors are to be synchronized with said processor,an okay to synchronize circuit connected to a corresponding line of said synchronization bus for generating an okay to synchronize signal on said corresponding line of said synchronization bus when said processor is ready to fetch a next instruction,a synchronization logic unit connected to said synchronization bus, said program counter register and said synchronization register for inhibiting the fetching said next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus, thereafter permitting said fetching of said next instruction by said program counter resister,an execution unit for executing fetched instructions, whereby each processor is synchronized to said other of said processors indicated in said synchronization register on an instruction by instruction basis,a synchronization flag memory connected to said synchronization control logic having stored therein an indication of whether said processor is in a synchronized mode or in an unsynchronized mode, andwherein said synchronization logic unitinhibits the fetching the next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus when said synchronization flag memory indicates said synchronized mode, andpermits the fetching of the next instruction by said program counter register regardless of the status of said synchronization bus and said synchronization register when said synchronization flag memory indicates said unsynchronized mode.
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Abstract
There is disclosed a multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.
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Citations
15 Claims
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1. A synchronization system comprising:
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a synchronization bus having a plurality of bus lines; a plurality of processors, equal in number to the number of bus lines in said synchronization bus, each processor fetching and executing instructions independently of other processors, each processor including a program counter register storing an address of a next instruction for fetching said next instruction; a synchronization register having a plurality of bits equal in number to the number of processors, each bit corresponding to a unique one of said plurality of processors, said synchronization register having stored therein an indication of which if any other of said processors are to be synchronized with said processor, an okay to synchronize circuit connected to a corresponding line of said synchronization bus for generating an okay to synchronize signal on said corresponding line of said synchronization bus when said processor is ready to fetch a next instruction, a synchronization logic unit connected to said synchronization bus, said program counter register and said synchronization register for inhibiting the fetching said next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus, thereafter permitting said fetching of said next instruction by said program counter resister, an execution unit for executing fetched instructions, whereby each processor is synchronized to said other of said processors indicated in said synchronization register on an instruction by instruction basis, a synchronization flag memory connected to said synchronization control logic having stored therein an indication of whether said processor is in a synchronized mode or in an unsynchronized mode, and wherein said synchronization logic unit inhibits the fetching the next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus when said synchronization flag memory indicates said synchronized mode, and permits the fetching of the next instruction by said program counter register regardless of the status of said synchronization bus and said synchronization register when said synchronization flag memory indicates said unsynchronized mode. - View Dependent Claims (2, 3, 4)
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5. A synchronization system comprising:
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a synchronization bus having a plurality of bus lines; a plurality of processors, equal in number to the number of bus lines in said synchronization bus, each processor fetching and executing instructions independently of other processors, each processor including a program counter register storing an address of a next instruction for fetching said next instruction; a synchronization register having a plurality of bits equal in number to the number of processors, each bit corresponding to a unique one of said plurality of processors, said synchronization register having stored therein an indication of which if any other of said processors are to be synchronized with said processor, an okay to synchronize circuit connected to a corresponding line of said synchronization bus for generating on said corresponding line of said synchronization bus an okay to synchronize signal when said processor is ready to fetch a next instruction, a synchronization flag memory having stored therein an indication of whether said processor is in a synchronized mode or in an unsynchronized mode, a synchronization logic unit connected to said synchronization bus, said program counter register, said synchronization register and said synchronization flag memory, said synchronization logic unit including means for inhibiting the fetching said next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus when said synchronization flag memory indicates said synchronized mode and thereafter permitting fetching of said next instruction by said program counter register, means for permitting the fetching of said next instruction by said program counter register regardless of the status of said synchronization bus and said synchronization register when said synchronization flag memory indicates said unsynchronized mode, and an execution unit for executing fetched instructions, whereby each processor is synchronized to said other of said processors indicated in said synchronization register on an instruction by instruction basis. - View Dependent Claims (6, 7, 8, 9)
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10. The method of operating a computer system having a plurality of processors in synchronism, each of the processors independently fetching and executing instructions, said method comprising the steps of:
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storing at each processor an indication of a synchronized mode or an unsynchronized mode; storing at each processor an indication of other processor or processors to which said processor is to be synchronized; generating at each processor a ready signal when said processor is ready to fetch an instruction; inhibiting fetching an instruction at each processor until said processor receives said ready signal from all processors to which that processor is to be synchronized according to said stored indication when said processor stores an indication of the synchronized mode and thereafter permitting fetching said instruction at each processor; permitting fetching an instruction at each processor regardless of the status of the ready signal of other processors when said processor stores an indication of the unsynchronized mode; and executing fetched instructions at each processor, whereby each processor is synchronized with said other processor or processors according to said stored indication on an instruction by instruction basis. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification