Computer module having removable remotely programmable non-volatile memory

• US 6,038,640 A
• Filed: 04/24/1997
• Issued: 03/14/2000
• Est. Priority Date: 04/25/1996
• Status: Expired due to Term

• Current Assignee: Airbus Operations SAS (Airbus SE)
• Original Assignee: Aerospatiale Societe Nationale Industrielle
• Inventors: Terme, Jean-Louis
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US08/847,382
• Time in Patent Office: 1,055 Days
• Field of Search: 361/790, 365/52, 395/750.05, 705/403, 711/164, 711/115, 711/103, 711/163, 701/24, 701/99, 701/115, 713/200, 710/13, 710/62
• US Class Current: 711/115
• CPC Class Codes: G06F 8/60 Software deployment

Abstract

Computational rig (20) consisting of two distinct parts (2, 21), linked together in a removable manner by cooperating contactors (9, 16), said parts respectively including the central processing unit (6) and a non-volatile memory block (12A) supporting the software program of said computational rig.

According to the invention, said non-volatile memory (12A) is electrically erasable and programmable and the part (21) moreover includes:

a memory (22) supporting a program for loading said software program into the memory block (12A);

means (23) of connection of the part (21) to a communication channel (24); and

a bidirectional communication peripheral device (25), arranged between the means of connection (23) and the loading memory (22).

Claims

1. A computational rig (20) comprising:

a first part (2) including;

a central processing unit (6);

first connection means (9); and

a first electronic interface device (7) arranged between said first connection means and said central processing unit; and

a second part (21) linked to said first part (2) in a removable manner so that said second part (21) may be removed from said first part without removal of a housing of said first part, said second part (21) including;

a memory block (12A) comprising at least one electrically erasable and programmable non-volatile memory;

at least part of a software program of said computational rig being stored in said memory block (12A);

second connection means (16) complementary to said first connection means;

a second electronic interface device (13A) arranged between said second connection means and said memory block and able to cooperate with said first electronic interface device through said first and second connection means;

a loading memory (22) associated with said memory block (12A);

a loading program associated with said loading memory (22) for entering said software program into said memory block (12A);

third connection means (23) allowing the connection of said second part (21) to a communication channel (24); and

a bidirectional communication peripheral device (25), arranged between said third connection means (23) and said loading memory (22) and serving as support in the loading of said software program,

said second part (21) additionally comprising;

fourth connection means (31) making it possible to receive information for authorizing loading of said software program into said loading memory (22);

a authorization information acquisition peripheral device (32), linked to said fourth connection means (31); and

a logic device (28), linked to said authorization information acquistion peripheral device (32), which authorizes the loading of said software program into said loading memory (22) only when said authorization information is present via said fourth connection means (31).

2. The computational rig as claimed in claim 1, wherein said logic device (28) authorizes operation of said second peripheral device (32) only when said authorization information is present via said fourth connection means (31).

3. The computational rig as claimed in claim 1, wherein said loading memory (22) is distinct from said memory block (12A).

4. The computational rig as claimed in claim 1, wherein said loading memory (22) forms part of said memory block (12A) and is reprogrammable.

5. The computational rig as claimed in claim 1, wherein said first part (2) is enclosed in a first box (4), wherein said second part (21) is enclosed in a second box (11), wherein said first connection means (9) is mounted on said first box (4), wherein said second connection means (16) is mounted on said second box (11), so that said second part (21) forms a plug-in module for said first part (2).

6. The computational rig as claimed in claim 5, wherein said first box (4) of said first part (2) includes a housing (5) with which said second box (11) of said second part (21) can be interlocked.