Single-chip data processor handling synchronous and asynchronous exceptions by branching from a first exception handler to a second exception handler

• US 6,038,661 A
• Filed: 09/07/1995
• Issued: 03/14/2000
• Est. Priority Date: 09/09/1994
• Status: Expired due to Term

• Current Assignee: Advanced Processor Technologies LLC (Acacia Research Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Yoshioka, Shinichi, Matsui, Shigezumi, Narita, Susumu, Kawasaki, Ikuya
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US08/524,712
• Time in Patent Office: 1,650 Days
• Field of Search: 395/800, 395/733, 395/742, 395/591, 395/800.01, 395/800.02, 395/800.32, 395/734, 364/230.2, 364/263.2, 364/280.8, 711/200, 710/260-269, 712/244, 712/32
• US Class Current: 712/244
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence

Abstract

A vector point of an exception handler related to TLB miss exception events is obtained by reading a vector base address of a register VBR one time, and by adding a vector offset (H'"'"'400) thereto. A vector point of an exception handler related to exception events other than the TLB miss exception events is obtained by adding a vector offset to a value (vector base address) of the register VBR, and an exception code which is an address offset obtained by reading a value of the register EXPEVT or INTEVT one time is added to the vector point that is obtained. Thus, the processing is branched to a required exception handler to execute the exception event processing related to exception events other than the TLB miss exception events.

Claims

1. A single-chip data processor comprising:

a central processing unit; and

a storage circuit, adapted for storing an exception code in response to an exception event, wherein the exception code corresponds to the exception event, comprising;

a first portion adapted for storing the exception code corresponding to a first type of exception event that occurs synchronously with the operation of the central processing unit; and

a second portion adapted for storing the exception code corresponding to a second type of exception event that occurs asynchronously with the operation of the central processing unit; and

wherein the central processing unit includes;

a program counter;

a plurality of general purpose registers;

a base register storing a vector base address, the vector base address representing a start address of a vector table corresponding to a plurality of exception handlers, wherein the vector base address is changeable in response to a program executed by the central processing unit, and

a control unit which, in response to the occurrence of an exception event, writes a first instruction address into the program counter based on the vector base address and a predetermined vector offset, wherein the predetermined vector offset is assigned in advance to the exception event and provided in response to the exception event so that a first exception handler assigned to the first instruction address may be executed,

wherein the central processing unit calculates a second instruction address of a second exception handler from the first exception handler by utilizing the exception code stored in the storage circuit as an address offset without the calculation effecting the plurality of general purpose registers.

2. A single-chip data processor according to claim 1, wherein the central processing unit further comprises:

a status register for storing internal conditions of the data processor;

a first saved register into which, in response to the occurrence of an exception event, the internal conditions are stored in the status register and

a second saved register into which, in response to the occurrence of the exception event, a return instruction address is stored, wherein the return instruction address corresponds to an instruction that is to be executed after completion of processing of the exception event.

3. A single-chip data processor according to claim 2, wherein the central processing unit further comprises:

an arithmetic and logic operation unit, and

a constant generating unit which generates the predetermined vector offset in response to the occurrence of the exception event,

wherein the arithmetic and logic operation unit adds the vector base address and the predetermined vector offset to generate the first instruction address under control of the control unit.

4. A data processor according to claim 3, wherein the status register includes:

a first control bit that stores operating state data representing whether the single-chip data processor is in a user state in which a user program is running or in a supervisor state in which a system program is running; and

a second control bit that stores mask data representing whether to accept or mask other exception events that follow the exception event,

wherein the control unit saves the internal conditions and the return instruction address in the first saved register and in the second saved register, respectively, and sets to the first control bit the operating state data representing the supervisor state and to the second control bit the mask data representing that the other exception events that follow the exception event are to be masked, wherein operation of the central processing unit branches to the first exception handler assigned to the first instruction address.

5. A single-chip data processor according to claim 4,

wherein the control unit sets mask data to the second control bit according to a processing specified in the first exception handler and saves the contents of the first and the second saved registers in a memory when the data set to the second control bit is mask data representing the acceptance of other exception events that follow the exception event.

6. A single-chip data processor according to claim 1, wherein the

central processing unit includes:

a first saved register;

a second saved register;

a status register including a first control bit and a second control bit;

an instruction break address register storing an instruction address specifying a break point; and

an instruction break controller which generates an instruction break exception event when an instruction corresponding to the instruction address stored in the instruction break address register is executed by the central processing unit,

wherein when the instruction break exception event is detected in a state where the mask data stored in the second control bit represents masking other exception events that follow the exception event, the control unit controls a branch to an instruction break exception handler without saving the internal conditions and the return instruction address in the first and the second saved registers, and

wherein the instruction break exception handler calculates a return instruction address from the instruction break exception handler by utilizing an instruction address stored in the instruction break address register after the internal conditions and the return instruction address are saved in the memory, and writes the calculated return instruction address into the second saved register, wherein the instruction break exception event is processed with the instruction break exception handler in a state where multiple exception events are masked.

7. A single-chip data processor according to claim 6,

wherein when a third exception event other than the instruction break exception event is detected in a state where the mask data stored in the second control bit represents masking other exception events that follow the exception event, the control unit controls a branch to a handler of reset exception after the exception code is stored in the storage circuit, and, when a fourth exception event is detected, masks acceptance of the fourth exception event until the masking for the multiple acceptance of the exception events is reset.

8. A single-chip data processor according to claim 4, wherein the central processing unit further comprises:

first and second general-purpose register sets constituting a plurality of banks, wherein one of the first and second general-purpose register sets is used as a general-purpose register set in the supervisor state and the other of the first and second general-purpose register sets is used as a general-purpose register set in the user state.

9. A single-chip data processor comprising:

a central processing unit;

an exception register for storing an exception code in response to occurrence of an exception event, the exception code corresponding to the exception event that has occurred, wherein the exception event is a predetermined type of exception event, the exception register having a first portion corresponding to a first predetermined type of exception event that occurs synchronously with the operation of the central processing unit and having a second portion corresponding to a second type of exception event that occurs asynchronously with the operation of the central processing unit; and

the central processing unit including;

a program counter;

a plurality of general purpose registers;

a vector base address register storing a vector base address, wherein the vector base address is changeable in response to a program executed by the central processing unit;

a circuit responsive to an exception event and forming a vector offset from a number of vector offsets depending upon the type of the exception event, wherein the number of vector offsets is smaller than the number of exception events and wherein the vector offsets are fixed offsets to the vector base address for calculating vector addresses; and

an arithmetic and logic unit for adding the vector base address and the vector offset and storing a calculated value in the program counter so that processing of the single-chip data processor branches to a first exception handler specified by the calculated value,

wherein the central processing unit calculates a first instruction address of a second exception handler from the first exception handler utilizing the exception code stored in the exception register as an address offset without the calculation effecting the plurality of general purpose registers.

10. A single-chip data processor according to claim 9, further comprising:

a memory management unit having an address translation look-aside buffer,

wherein the vector offset comprises a first vector offset assigned to a plurality of interrupt events, wherein a second vector offset is assigned to address translation look-aside buffer miss exception events, and wherein a third vector offset is assigned to general exception events other than the address translation look-aside buffer miss exception events.

11. A single-chip data processor according to claim 10, wherein the exception register is provided in the memory management unit.

12. A single-chip data processor comprising:

a central processing unit;

an address translation look-aside buffer controller including;

a storage circuit, adapted for storing an exception code in response to an exception event, wherein the exception code corresponds to the exception event, comprising;

a first portion adapted for storing the exception code corresponding to a first type of exception event that occurs synchronously with the operation of the central processing unit; and

a second portion adapted for storing the exception code corresponding to a second type of exception event that occurs asynchronously with the operation of the central processing unit; and

the central processing unit including;

a program counter;

a plurality of general purpose registers;

a base register storing a vector base address, the vector base address representing a start address of a vector table corresponding to a plurality of exception handlers, wherein the vector base address is changeable in response to a program executed by the central processing unit, and

a control unit which, in response to the occurrence of an exception event, writes a first instruction address into the program counter based on the vector base address and a predetermined vector offset, wherein the predetermined vector offset is assigned in advance to the exception event and provided in response to the exception event so that a first exception handler assigned to the first instruction address may be executed,

wherein the storage circuit holds the exception code so that the central processing unit can calculate a second instruction address of a second exception handler from the first exception handler by utilizing the exception code as an address offset without the calculation effecting the plurality of general purpose registers.

13. A single-chip data processor comprising:

a central processing unit;

an exception register storing an exception code in response to occurrence of an exception event, the exception code corresponding to the exception event that has occurred, the exception register having a first portion corresponding to a first predetermined type of exception event that occurs synchronously with the operation of the central processing unit and having a second portion corresponding to a second type of exception event that occurs asynchronously with the operation of the central processing unit; and

the central processing unit including;

a program counter;

a plurality of general purpose registers;

a vector base address register storing a vector base address, wherein the vector base address is changeable in response to a program executed by the central processing unit;

a circuit responsive to an exception event and determining a vector offset depending upon the type of the exception event;

an arithmetic and logic unit, wherein the arithmetic and logic unit calculates a first address of a first exception handler based on the vector base address and the vector offset, wherein processing of the single-chip data processor branches to the first exception handler;

wherein the central processing unit calculates a first instruction address of a second exception handler from the first exception handler utilizing the exception code stored in the exception register as an address offset without the calculation effecting the plurality of general purpose registers.

14. A single-chip data processor according to claim 13, further comprising:

a memory management unit having an address translation look-aside buffer,

wherein the vector offset comprises a first vector offset assigned to a plurality of interrupt events, wherein a second vector offset is assigned to address translation look-aside buffer miss exception events, and wherein a third vector offset is assigned to general exception events other than the address translation look-aside buffer miss exception events.

15. A single-chip data processor according to claim 13, wherein the exception register is provided in a memory management unit coupled to the central processing unit.