Two square NVRAM cell

• US 6,040,218 A
• Filed: 09/13/1999
• Issued: 03/21/2000
• Est. Priority Date: 06/19/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lam, Chung H.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/394,093
• Time in Patent Office: 190 Days
• Field of Search: 438/259, 438/270, 438/589
• US Class Current: 438/259
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile random access memory (NVRAM) cell and method of fabrication thereof. Pairs of NVRAM cells, each including three FETs stacked in a NAND-like structure are formed vertically in silicon pillars. Source devices at the bottom of the pillar selectively provide ground to one of the cells. A floating gate extends upward from the source device'"'"'s gate line. A control gate plate extending between adjacent pillars selectively provides a programming voltage to the control gate. Both the source gate and the control gate are capacitively coupled through silicon rich oxide to the floating gate. Polysilicon plugs between silicon pillars are word line gates for cells in adjacent pillars. A diffusion at the top of each pillar is a bit line contact for both cells at the pillar. Each pair of cells on a pillar are on a common bit line and a common word line. The word line, control gate and source gate line select individual cells in the pair.

Claims

1. A method of forming an array of non-volatile random access memory (NVRAM) cells comprising the steps of:

a) etching a plurality of trenches in a semiconductor layer;

b) forming a source gate line of a first conductive material in said trenches;

c) forming sidewalls of said first conductive material above said source gate line along the sidewalls of said trenches;

d) forming a plate of a second conductive material between said first conductive material sidewalls;

e) plugging said trenches above said plate with said first conductive material;

f) forming perpendicular to said trenches a plurality of second trenches, said second trenches dividing said trenches such that semiconductor pillars are formed, said first conductive material sidewalls are divided into floating gates adjacent said semiconductor pillars and said first conductive material plugging said trenches is divided into word line plugs adjacent said semiconductor pillars.

2. The method of claim 1 wherein the step (b) of forming the source gate line comprises the steps of:

1) implanting diffusion into the bottom of said trench;

2) forming a gate oxide layer on the sidewalls of said trenches;

3) filling said trenches with said first conductive material;

4) etching said first conductive material from said trenches until a source gate line of said first conductive material remains in said trenches.

3. The method of claim 2, wherein the first conductive material is etched in the etching step (4) such that a pillar of said first conductive material remains extending above said semiconductor material in each said trench from said source gate line.

4. The method of claim 2, wherein the step (c) of forming first conductive material sidewalls comprises the steps of:

1) forming an oxide layer on said source gate line and a gate oxide layer on the sidewalls of said trenches;

2) depositing a first layer of said first conductive material;

3) implanting said semiconductor material into said oxide layer;

4) depositing a conformal layer of said first conductive material; and

5) directionally etching said conformal layer along said sidewall below said semiconductor sidewalls.

5. The method of claim 2, wherein the step (d) of forming the second conductive material plate comprises the steps of:

1) forming a thin conformal liner of said first conductive material;

2) oxidizing horizontal portions of said thin conformal liner

3) filling said liner with said second conductive material.

6. The method of claim 5, wherein the step (d) further comprises the steps of:

4) etching said second conductive material and said thin conformal liner into said trenches below the top edge of said first material sidewalls.

7. The method of claim 6, wherein the second conductive material and thin first conductive material are etched in the etching step (4) such that a pillar of said second conductive material remains extending above said semiconductor material in each said trench from said second conductive material plate.

8. The method of claim 2, further comprising the steps of:

g) forming bit line diffusions at each pillar'"'"'s top surface;

h) in each column, connecting all bit line diffusions together; and

i) in each row, connecting all word line plugs together.

9. The method of claim 2 wherein the semiconductor material is silicon, the first conductive material is polysilicon and the second conductive material is silicide.