Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits

• US 6,040,223 A
• Filed: 08/13/1999
• Issued: 03/21/2000
• Est. Priority Date: 08/13/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Meng-Chang, Yen, Ming-Shu, Chiu, Fu-Ying, Su, Su-Ying, Lin, Chien-Hung, Lin, Jyh-Feng
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): CHEN, JACK S J
• Application Number:
  US09/373,636
• Time in Patent Office: 221 Days
• Field of Search: 438/286, 438/301, 438/303, 438/305, 438/306, 438/307, 438/521, 438/585, 438/586, 438/595
• US Class Current: 438/303
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for making improved polysilicon FET gate electrodes having composite sidewall spacers is achieved. After forming the polysilicon gate electrodes on the substrate, a SiO₂ stress-release layer is deposited having a trapezoidal shape. A Si₃ N₄ layer is deposited and plasma etched back using the SiO₂ layer as an etch-endpoint-detect layer to form composite sidewall spacers that include portions of the trapezoidal-shaped oxide layer. The SiO₂ layer protects the source/drain areas from plasma etch damage that could cause high leakage currents. The Si₃ N₄ also extends over the SiO₂ layer at the upper edges of the polysilicon gate electrodes. This prevents erosion of the SiO₂ along the gate electrodes when the remaining oxide is removed from the source/drain areas using hydrofluoric acid wet etching. When an insulating layer is deposited over the FETs, and self-aligned contact openings are etched to the source/drain areas and extending over the gate electrodes, the Si₃ N₄ extending over the portion of the trapezoidal-shaped SiO₂ layer that forms part of the composite sidewall spacer protects the SiO₂ from etching. This results in more reliable contacts without degrading the FET performance.

Claims

1. A method for making FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer comprising the steps of:

providing a semiconductor substrate having device areas surrounded and electrically isolated by field oxide areas;

forming a gate oxide on said device areas;

depositing a polysilicon layer on said device areas and elsewhere on said substrate, said polysilicon layer being conductively doped;

patterning said polysilicon layer to form said FET gate electrodes on said device areas;

forming lightly doped source/drain areas adjacent to said FET gate electrodes;

depositing a first insulating layer on said FET gate electrodes, said first insulating layer having a trapezoidal shape over said FET gate electrodes such that only the top edges of said FET gate electrodes are free of said first insulating layer;

depositing a conformal second insulating layer on said first insulating layer;

anisotropically plasma etching said second insulating layer to said first insulating layer to form said sidewall spacers on sidewalls of said FET gate electrodes, said first insulating layer acting as an etch endpoint detect;

removing said first insulating layer remaining on said lightly doped source/drain areas using a wet etch, while said second insulating layer protects said first insulating layer at top edges of said FET gate electrodes;

forming source/drain contact areas adjacent to said sidewalls of said FET gate electrodes in said device areas;

depositing a blanket third insulating layer on said substrate and planarizing;

etching contact openings in said third insulating layer to said source/drain contact areas, while said second insulating layer protects said first insulating layer at top edges of said FET gate electrodes when etching said contact openings that extend over said FET gate electrodes.

2. The method of claim 1, wherein said gate oxide is formed by thermal oxidation to a thickness of between about 40 and 100 Angstroms.

3. The method of claim 1, wherein said polysilicon layer is deposited to a thickness of between about 800 and 2000 Angstroms and is conductively doped to a concentration of between about 1.0 E 18 and 1.0 E 20 atoms/cm³.

4. The method of claim 1, wherein said first insulating layer is silicon oxide deposited by high-density plasma chemical vapor deposition to a thickness of between about 100 and 500 Angstroms on horizontal surfaces of said substrate, while concurrently DC biasing said substrate during deposition to achieve a silicon oxide etch rate to silicon oxide deposition rate having a ratio equal to about 1 at said top edges of said FET gate electrodes.

5. The method of claim 1, wherein said first insulating layer is silicon oxide deposited conformally by chemical vapor deposition and subsequently subjected to sputter etching in an inert gas to achieve a final thickness of between about 100 and 500 Angstroms on horizontal surfaces of said substrate, while said sputter etching results in enhanced etching at top edges of said FET gate electrodes thereby achieving said trapezoidal-shaped insulating layer.

6. The method of claim 1, wherein said second insulating layer is silicon nitride deposited to a thickness of between about 300 and 3000 Angstroms.

7. The method of claim 6, wherein said silicon nitride is anisotropically plasma etched using high-density plasma etching and an etchant gas mixture of CF₄, CHF₃, O₂, N₂, CO, C₄ F₈, and Ar.

8. The method of claim 1, wherein said wet etch is a dilute solution of hydrofluoric acid and water having a ratio by volume of about 1:

100.

9. The method of claim 1, wherein said third insulating layer is silicon oxide deposited by chemical vapor deposition and is planarized to a thickness of between about 6000 and 12000 Angstroms.

10. The method of claim 1, wherein said contact openings are anisotropically plasma etched using high-density plasma etching and an etchant gas mixture of CF₄, CHF₃, O₂, N₂, CO, C₄ F₈, and Ar that achieves an etch-rate selectivity of said first insulating layer to said second insulating layer of greater than about 10:

1.

11. A method for making FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer comprising the steps of:

providing a semiconductor substrate having device areas surrounded and electrically isolated by field oxide areas;

forming a gate oxide on said device areas;

depositing a polysilicon layer on said device areas and elsewhere on said substrate, said polysilicon layer being conductively doped;

patterning said polysilicon layer to form said FET gate electrodes on said device areas;

forming lightly doped source/drain areas adjacent to said FET gate electrodes;

depositing a first insulating layer composed of silicon oxide on said FET gate electrodes, said first insulating layer having a trapezoidal shape over said FET gate electrodes such that only the top edges of said FET gate electrodes are free of said first insulating layer;

depositing a conformal second insulating layer composed of silicon nitride on said first insulating layer;

anisotropically plasma etching said second insulating layer to said first insulating layer to form said sidewall spacers on sidewalls of said FET gate electrodes, said first insulating layer acting as an etch endpoint detect;

removing said first insulating layer remaining on said lightly doped source/drain areas using a hydrofluoric acid wet etch, while said second insulating layer protects said first insulating layer at top edges of said FET gate electrodes;

forming source/drain contact areas adjacent to said sidewalls of said FET gate electrodes in said device areas;

depositing a blanket third insulating layer on said substrate and planarizing;

etching contact openings in said third insulating layer to said source/drain contact areas, while said second insulating layer protects said first insulating layer at top edges of said FET gate electrodes when etching said contact openings that extend over said FET gate electrodes.

12. The method of claim 11, wherein said gate oxide is formed by thermal oxidation to a thickness of between about 40 and 100 Angstroms.

13. The method of claim 11, wherein said polysilicon layer is deposited to a thickness of between about 800 and 2000 Angstroms and is conductively doped to a concentration of between about 1.0 E 18 and 1.0 E 20 atoms/cm³.

14. The method of claim 11, wherein said first insulating layer composed of silicon oxide is deposited by high-density-plasma chemical vapor deposition to a thickness of between about 100 and 500 Angstroms on horizontal surfaces of said substrate, while concurrently DC biasing said substrate during deposition to achieve a silicon oxide etch rate to silicon oxide deposition rate having a ratio equal to about 1 at said top edges of said FET gate electrodes.

15. The method of claim 11, wherein said first insulating layer composed of silicon oxide is conformally deposited by chemical vapor deposition and subsequently subjected to sputter etching in an inert gas to achieve a final thickness of between about 100 and 500 Angstroms on horizontal surfaces of said substrate, while said sputter etching results in enhanced etching at top edges of said FET gate electrodes thereby achieving said trapezoidal-shaped insulating layer.

16. The method of claim 11, wherein said second insulating layer composed of silicon nitride is deposited to a thickness of between about 300 and 3000 Angstroms.

17. The method of claim 11, wherein said silicon nitride is anisotropically plasma etched using high-density plasma etching and an etchant gas mixture of CF₄, CHF₃, O₂, N₂, CO, C₄ F₈, and Ar.

18. The method of claim 11, wherein said hydrofluoric acid wet etch is a dilute solution of hydrofluoric acid and water having a ratio by volume of about 1:

100.

19. The method of claim 11, wherein said third insulating layer is silicon oxide deposited by chemical vapor deposition and is planarized to a thickness of between about 6000 and 12000 Angstroms.

20. The method of claim 11, wherein said contact openings are anisotropically plasma etched using high-density plasma etching and an etchant gas mixture of CF₄, CHF₃, O₂, N₂, CO, C₄ F₈, and Ar that achieves an etch-rate selectivity of silicon oxide to silicon nitride of greater than about 10:

1.