Method of avoiding sidewall residue in forming connections

• US 6,040,241 A
• Filed: 02/11/1998
• Issued: 03/21/2000
• Est. Priority Date: 02/11/1998
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chern, Horng-Nan, Lee, Tzung-Han
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): NGUYEN, THANH T
• Application Number:
  US09/021,750
• Time in Patent Office: 769 Days
• Field of Search: 438/622, 438/257-267, 438/275, 438/283, 438/303, 438/305, 438/592
• US Class Current: 438/622
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Abstract

The method in the present invention for forming insulation over conductor includes the following steps. At first, a substrate with a first conductor formed over is provided. The first conductor can be either a gate structure or an interconnection layer. A dielectric layer is then formed over the first conductor the substrate. A portion of the dielectric layer is removed for having a recess free sidewall on the dielectric layer around the first conductor. An insulation for succeeding conductive layer is formed.

Claims

1. A method for forming insulation over conductor, said method comprising the steps of:

providing a substrate with a gate structure formed over, wherein said gate structure includes;

a polysilicon layer over said substrate;

a tungsten silicide layer over said polysilicon layer;

an upper insulator layer over said tungsten silicide layer; and

insulator spacers with a recessed region covering conformably on sidewalls of said upper insulator layer, said tungsten silicide layer and said polysilicon layer;

forming a dielectric layer over said gate structure and said substrate; and

performing an etching back process to remove a portion of said dielectric layer for thinning said dielectric layer and having a recess free sidewall on said dielectric layer around said gate structure.

2. The method of claim 1, wherein said method further comprising the steps of

forming a conductor over said dielectric layer;

and

removing a portion of said conductor to define a conductor pattern.

3. The method of claim 2, wherein said conductor comprises a combination of conductive layers to serve as an interconnection layer.

4. The method of claim 1, wherein said recessed region on sidewall is due to said narrower tungsten silicide layer formed by clean process before said insulator spacer formed.

5. The method of claim 1, wherein said dielectric layer comprises an oxide layer.

6. The method of claim 5, wherein said oxide layer is formed by chemical vapor deposition with a reaction gas of tetra-ethyl-ortho-silicate (TEOS).

7. The method of claim 1, wherein said dielectric layer comprises at least two oxide layers.

8. A method for forming connection, said method comprising the steps of:

providing a substrate with a gate structure formed over, wherein said gate structure includes;

a polysilicon layer over said substrate;

a tungsten silicide layer over said polysilicon layer;

an upper insulator layer over said tungsten silicide layer; and

nitride spacers with a recessed region covering conformably on sidewalls of said upper insulator layer, said tungsten silicide layer and said polysilicon layer;

forming a dielectric layer over said gate structure and said substrate;

performing an etching back process to remove a portion of said dielectric layer for thinning said dielectric layer and having a recess free sidewall on said dielectric layer around said gate structure;

forming a conductor over said dielectric layer; and

removing a portion of said conductor to define a conductor pattern.

9. The method of claim 8, wherein said recessed region on sidewall is due to said narrower tungsten silicide layer formed by clean process before said insulator spacer formed.

10. The method of claim 8, wherein said conductor comprises a combination of conductive layers to serve as an interconnection layer.

11. The method of claim 8, wherein said dielectric layer comprises an oxide layer.

12. The method of claim 8, wherein said oxide layer is formed by chemical vapor deposition with a reaction gas of tetra-ethyl-ortho-silicate (TEOS).

13. The method of claim 8, wherein said dielectric layer comprises at least two oxide layers.