Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion

• US 6,040,243 A
• Filed: 09/20/1999
• Issued: 03/21/2000
• Est. Priority Date: 09/20/1999
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Zhou, Mei-Sheng, Li, Jianxun, Chooi, Simon
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/398,292
• Time in Patent Office: 183 Days
• Field of Search: 438/687, 438/622, 438/627, 438/629, 438/692, 438/624, 438/631, 438/633, 438/637, 438/639, 438/672, 438/666
• US Class Current: 438/687
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76844 Bottomless liners

Abstract

A method of fabricating damascene vias has been achieved. Diffusion of copper into dielectric layers due to overetch of the passivation layer is eliminated by a barrier layer. The method can be used to form dual damascene interconnects. Copper traces through an isolation layer are provided overlying a semiconductor substrate. A passivation layer is deposited overlying the copper traces and the isolation layer. A dielectric layer is deposited. A cap layer is deposited. The cap layer and the dielectric layer are patterned to expose the top surface of the passivation layer and to form trenches for the damascene vias. A barrier layer is deposited overlying the passivation layer, the dielectric layer, and the cap layer. The barrier layer is etched though to expose the top surfaces of the cap layer and the passivation layer. The barrier layer isolates the sidewalls of the trenches. The passivation layer is etched through to complete damascene vias. The barrier layer prevents copper sputtering onto the dielectric layer during the step of etching through the passivation layer.

Claims

1. A method to prevent copper diffusion into dielectric layers in the fabrication of a damascene via in the manufacture of an integrated circuit device comprising:

providing copper traces through an isolation layer overlying a semiconductor substrate;

depositing a passivation layer overlying said copper traces and said isolation layer;

depositing a dielectric layer overlying said passivation layer;

depositing a cap layer overlying said dielectric layer;

patterning said cap layer and said dielectric layer to form an opening for planned said damascene via and to expose the top surface of said passivation layer overlying said copper traces;

depositing a barrier layer overlying said passivation layer and said dielectric layer;

etching through said barrier layer to expose the top surfaces of said passivation layer and said cap layer wherein remaining said barrier layer isolates sidewalls of said opening; and

etching through said passivation layer to the top surface of said copper traces to complete said damascene via in the manufacture of said integrated circuit device.

2. The method according to claim 1 wherein said passivation layer comprises silicon nitride.

3. The method according to claim 1 wherein said dielectric layer comprises one of the group of:

silicon dioxide, fluorinated silicon dioxide, hydrogen-doped silicon dioxide, carbon and hydrogen-doped silicon dioxide, fluorinated organic polymer, and non-fluorinated organic polymer.

4. The method according to claim 1 wherein said cap layer comprises silicon nitride.

5. The method according to claim 1 wherein said barrier layer comprises one of the group of:

metals, metal nitrides, metal silicon nitrides, metal boron nitrides, and metal oxides.

6. The method according to claim 1 wherein said step of etching through said barrier layer to expose the top surfaces of said passivation layer and said cap layer is by anisotropic reactive ion etching having a chemistry comprising:

chlorine (Cl₂), boron trichloride (BCl₃), carbon tetrafluoride (CF₄), sulfur hexafluoride (SF₆), and combinations of these gases.

7. The method according to claim 1 wherein said barrier layer is deposited to a thickness of between about 50 Angstroms and 2,000 Angstroms.

8. The method according to claim 1 wherein said barrier layer prevents copper sputtering onto said dielectric layer during said step of etching through said passivation layer.

9. A method to prevent copper diffusion into dielectric layers in the fabrication of dual damascene interconnects in the manufacture of an integrated circuit device comprising:

providing copper traces through an isolation layer overlying a semiconductor substrate;

depositing a passivation layer overlying said copper traces and said isolation layer;

depositing a dielectric layer overlying said passivation layer;

depositing a cap layer overlying said dielectric layer;

patterning said cap layer and said dielectric layer to expose the top surface of said passivation layer and to form interconnect trenches and via trenches for dual damascene interconnects overlying said copper traces;

depositing a barrier layer overlying said passivation layer, said dielectric layer, and said cap layer;

etching though said barrier layer to expose the top surfaces of said passivation layer and said cap layer wherein remaining said barrier layer isolates sidewalls of said interconnect trenches and via trenches;

etching through said passivation layer to expose the top surface of said copper traces;

depositing a copper layer overlying said cap layer, said barrier layer, and said copper traces, and completely filling said interconnect trenches and said via trenches; and

polishing down said copper layer to the top surface of said cap layer thereby completing said dual damascene interconnects in the manufacture of said integrated circuit device.

10. The method according to claim 9 wherein said passivation layer comprises silicon nitride.

11. The method according to claim 9 wherein said dielectric layer comprises one of the group of:

silicon dioxide, fluorinated silicon dioxide, hydrogen-doped silicon dioxide, carbon and hydrogen-doped silicon dioxide, fluorinated organic polymer, and non-fluorinated organic polymer.

12. The method according to claim 9 wherein said cap layer comprises silicon nitride.

13. The method according to claim 9 wherein said barrier layer comprises one of the group of:

metals, metal nitrides, metal silicon nitrides, metal boron nitrides, and metal oxides.

14. The method according to claim 9 wherein said barrier layer prevents copper sputtering onto said dielectric layer during said step of etching through said passivation layer.

15. The method according to claim 9 wherein said barrier layer comprises tungsten nitride and wherein said step of depositing said copper layer is by seedless electrochemical plating.

16. A method to prevent copper diffusion into dielectric layers in the fabrication of dual damascene interconnects in the manufacture of an integrated circuit device comprising:

providing copper traces through an isolation layer overlying a semiconductor substrate;

depositing a passivation layer of silicon nitride overlying said copper traces and said isolation layer;

depositing a first dielectric layer overlying said passivation layer;

depositing an etch stopping layer overlying said first dielectric layer;

depositing a second dielectric layer overlying said etch stopping layer;

depositing a cap layer overlying said second dielectric layer;

patterning said cap layer, said second dielectric layer, said etch stopping layer, and said first dielectric layer to expose the top surface of said passivation layer and to form interconnect trenches and via trenches for dual damascene interconnects overlying said conductive traces;

depositing a barrier layer of tungsten nitride overlying said passivation layer, said second dielectric layer, said etch stopping layer said cap layer, and said first dielectric layer;

etching though said barrier layer to expose the top surfaces of said passivation layer and said cap layer wherein remaining said barrier layer isolates sidewalls of said interconnect trenches and via trenches;

etching through said passivation layer to expose the top surface of said copper traces wherein said barrier layer prevents copper sputtering onto said first dielectric layer and said second dielectric layer;

depositing a copper layer by seedless electrochemical plating overlying said cap layer, said barrier layer, and said copper traces, and completely filling said via trenches and said interconnect trenches; and

polishing down said copper layer to the top surface of said cap layer thereby completing said dual damascene interconnects in the manufacture of said integrated circuit device.

17. The method according to claim 16 wherein said first dielectric layer comprise one of the group of:

silicon dioxide, phosphosilicate glass and polyimide.

18. The method according to claim 16 wherein said etch topping layer comprises silicon nitride.

19. The method according to claim 16 wherein said second dielectric layer comprise one of the group of:

silicon dioxide, fluorinated silicon dioxide, hydrogen-doped silicon dioxide, carbon and hydrogen-doped silicon dioxide, fluorinated organic polymer, and non-fluorinated organic polymer.

20. The method according to claim 16 wherein said cap layer comprises silicon nitride.