Structure of a non-destructive readout dynamic random access memory

• US 6,040,595 A
• Filed: 05/15/1998
• Issued: 03/21/2000
• Est. Priority Date: 03/13/1998
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Yang, Yu-Hao
• Primary Examiner(s): HARDY, DAVID B
• Application Number:
  US09/080,131
• Time in Patent Office: 676 Days
• Field of Search: 257/300, 257/301, 257/606
• US Class Current: 257/300
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A structure of dynamic random access memory includes a field effect transistor (FET), a capacitor, a world line and a bit line. The gate of the FET is electrically coupled to the word line in which a voltage source is supplied through the world line to the gate. The drain region of the FET is electrically coupled to a lower electrode of the capacitor. The capacitor has an upper electrode being electrically coupled to the gate of the FET either. The source region of the FET is electrically coupled to the bit line.

Claims

1. A structure of a circuit of a dynamic random access memory (DRAM), the structure of the circuit comprising:

a word line;

wherein the word line supplies a voltage source;

a bit line;

a capacitor;

wherein the capacitor in the DRAM is used for the storing a binary data and comprises a lower electrode and an upper electrode;

a field effect transistor (FET);

wherein the FET comprises a gate being electrically coupled to the word line, a source region being electrically coupled to the bit line and a drain region being electrically coupled to the lower electrode of the capacitor; and

a coupling structure of the capacitor, wherein the upper electrode of the capacitor is electrically coupled to the word line.

2. A structure of a dynamic random access memory (DRAM), the structure comprising:

a field effect transistor (FET), wherein the FET further comprises a gate, a source region and a drain region; and

a capacitor, wherein the capacitor further comprises a lower electrode and an upper electrode, in which the upper electrode is electrically coupled to the drain region.

3. The structure of claim 2, wherein the structure further comprises a bit line, which is electrically coupled to the source region of the FET.

4. The structure of claim 2, wherein the structure further comprises a word line, which is electrically coupled to the gate of the FET.

5. The structure of claim 2, wherein the gate is treated as the upper electrode.

6. A structure of a dynamic random access memory (DRAM), the structure comprising:

a field effect transistor (FET), wherein the FET further comprises a gate, a source region and a drain region;

a capacitor, wherein the capacitor further comprises a lower electrode and an upper electrode, in which the upper electrode is electrically coupled to the gate and the lower electrode is electrically coupled to the drain region;

a bit line, wherein the bit line is electrically coupled to the source region of the FET; and

a word line, wherein the word line is electrically coupled to the gate of the FET.

7. The structure of claim 6, wherein the gate is treated as the upper electrode.

8. A structure of a dynamic random access memory (DRAM), the structure comprising:

a substrate, wherein the substrate with a substrate surface comprises an opening below the substrate surface and an inner periphery of the opening;

a capacitor, wherein the capacitor is located in the opening and comprises a first electrode, a dielectric thin film and a second electrode, which are sequentially over the inner periphery of the opening;

an insulating layer;

wherein the insulating layer is over a portion of the capacitor and comprises an aperture to expose the second electrode;

a metal plug;

wherein the metal plug is electrically coupled to the second electrode through the aperture of the isolation layer;

a field effect transistor (FET), wherein the FET is on the substrate and comprises a gate, a source region and a drain region, in which the source region and the drain region is below the substrate surface; and

a coupling;

wherein the coupling comprises that the gate is electrically coupled to the second electrode through the metal plug and the drain region is electrically coupled to the first electrode.

9. A structure of a dynamic random access memory (DRAM), the structure comprising:

a substrate, wherein the substrate with a substrate surface comprises an opening below the substrate and an inner periphery of the opening;

a field effect transistor (FET), wherein the FET is on the substrate and comprises a gate, a source region and a drain region, in which the source region and the drain region is below the substrate surface and the gate is above the substrate surface;

a dielectric layer over the substrate and the gate, wherein the dielectric layer comprises a first opening to expose the gate and a second opening to expose the drain region;

a first electrode;

wherein the first electrode is over the dielectric layer around the second opening layer to be electrically coupled to the drain region through the second opening, but the first opening still exposes the gate;

a dielectric thin film over the first electrode; and

a second electrode;

wherein the second electrode covers the dielectric thin film and a portion of the dielectric layer, where comprises the first opening, so that the second electrode is electrically coupled to the gate through the first opening.

10. A dynamic random access memory (DRAM), comprising:

a substrate, wherein the substrate with a substrate surface comprises an opening below the substrate surface and an inner periphery of the opening;

a field effect transistor (FET), wherein the FET is on the substrate and comprises a gate, a source region and a drain region, in which the source region and the drain region is below the substrate surface and the gate is above the substrate surface;

a dielectric thin film over the substrate and the gate, wherein the dielectric thin film comprises a drain opening to expose the drain region; and

a conductive layer, wherein the conductive layer is located over the dielectric thin film and is electrically coupled to the drain region through the drain opening of the dielectric thin film.

11. The DRAM of claim 10, wherein the dielectric thin film has a thickness about between 10 and 60 Angstrom.

12. The DRAM of claim 10, wherein the dielectric thin film comprises silicon-dioxide/silicon-nitride/silicon-dioxide.

13. The DRAM of claim 10, wherein the dielectric thin film comprises Ta₂ O₅.

14. The DRAM of claim 10, wherein the dielectric thin film comprises PZT.

15. The DRAM of claim 10, wherein the dielectric thin film comprises BST.