Insulated trench semiconductor device with particular layer structure

• US 6,040,599 A
• Filed: 09/25/1996
• Issued: 03/21/2000
• Est. Priority Date: 03/12/1996
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US08/721,576
• Time in Patent Office: 1,273 Days
• Field of Search: 257/139, 257/143, 257/144, 257/153, 257/330, 257/331, 257/332, 257/311
• US Class Current: 257/330
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

It is an object to compatibly realize a decrease in an on-state voltage and an increase in a current capable of turn-off. An N layer (43) having an impurity concentration higher than that of an N^- layer (42) is formed between the N^- layer (42) and a P base layer (44). In the exposed surface of the P base layer (44) connected to an emitter electrode (51), a P⁺ layer (91) having an impurity concentration higher than that of the P base layer (44) is formed. The formation of the N layer (43) allows the carrier distribution in the N^- layer (42) to be close to the carrier distribution of a diode, so that the on-state voltage is decreased while maintaining high the current value capable of turn-off. Furthermore, the P⁺ layer (91) allows holes to easily go through form the P base layer (44) to the emitter electrode (51), which increases the current value capable of turn-off.

Claims

1. An insulated gate semiconductor device, comprising:

a first semiconductor layer of a first conductivity type having first and second main surfaces

a second semiconductor layer of a second conductivity type provided over the first main surface of said first semiconductor layer;

a third semiconductor layer of the second conductivity type provided in close contact on a surface of said second semiconductor layer and having an impurity concentration higher than the impurity concentration of said second semiconductor layer;

a fourth semiconductor layer of the first conductivity type provided in close contact on a surface of said third semiconductor layer;

a fifth semiconductor layer of the second conductivity type selectively provided in a surface of said fourth semiconductor layer;

a trench having an opening in a surface of said fifth semiconductor layer and having a depth extending through at least said fourth semiconductor layer from the surface of said fifth semiconductor layer;

an insulating film provided on an inner entire wall of said trench;

a control electrode provided in said trench to face said fourth semiconductor layer through said insulating film;

a first main electrode provided on the surface of said fourth and fifth semiconductor layers; and

a second main electrode provided on the second main surface of said first semiconductor layer, wherein said second semiconductor layer is thicker than said third semiconductor layer.

2. The insulated gate semiconductor device according to claim 1, wherein said trench has a depth extending also through said third semiconductor layer to reach said second semiconductor layer.

3. The insulated gate semiconductor device according to claim 1, wherein said trench has a depth limited in said third semiconductor layer.

4. The insulated gate semiconductor device according to claim 1, wherein said second semiconductor layer extends through said first semiconductor layer to be partially exposed in the second main surface of said first semiconductor layer.

5. The insulated gate semiconductor device according to claim 1, wherein a sixth semiconductor layer of the second conductivity type with an impurity concentration higher than the impurity concentration of said second semiconductor layer is provided between said first semiconductor layer and said second semiconductor layer.

6. The insulated gate semiconductor device according to claim 5, wherein said sixth semiconductor layer extends through said first semiconductor layer to be partially exposed in the second main surface of said first semiconductor layer.

7. The insulated gate semiconductor device according to claim 1, wherein said trench is divided into a plurality of unit trenches arranged side by side, and

an exposed surface of said fourth semiconductor layer is interposed between adjacent ones of said unit trenches.

8. The insulated gate semiconductor device according to claim 7, wherein the exposed surface of said fourth semiconductor layer is divided into a plurality of unit exposed surfaces by a part of said fifth semiconductor layer, the plurality of unit exposed surfaces being alternated with said part of said fifth semiconductor layer along said trench.

9. The insulated gate semiconductor device according to claim 8, wherein said first main electrode is connected to said fifth semiconductor layer only in said part.

10. The insulated gate semiconductor device according to claim 7, wherein

said fifth semiconductor layer is provided in the form of a plurality of belts parallel to each other in the surface of said fourth semiconductor layer, and

said plurality of unit trenches are provided along a direction intersecting said plurality of belts.

11. The insulated gate semiconductor device according to claim 1, wherein said fourth semiconductor layer has a seventh semiconductor layer of the first conductivity type at least in an exposed surface portion of said fourth semiconductor layer, and

an impurity concentration in said seventh semiconductor layer is higher than the impurity concentration in the portion in said fourth semiconductor layer outside of said seventh semiconductor layer.

12. The insulated gate semiconductor device according to claim 1, further comprising an eighth semiconductor layer of the first conductivity type formed to surround a bottom of said trench and having an impurity concentration higher than that in said second semiconductor layer.

13. An insulated gate semiconductor device, comprising:

a first semiconductor layer of a first conductivity type having first and second main surfaces;

a second semiconductor layer of a second conductivity type provided over the first main surface of said first semiconductor layer;

a third semiconductor layer of the second conductivity type provided in close contact on a surface of said second semiconductor layer and having an impurity concentration higher than the impurity concentration of said second semiconductor layer;

a fourth semiconductor layer of the first conductivity type provided in close contact on a surface of said third semiconductor layer;

a fifth semiconductor layer of the second conductivity type selectively provided in a surface of said fourth semiconductor layer;

a trench having an opening in a surface of said fifth semiconductor layer and having a trench depth extending through said fourth semiconductor layer and into said third semiconductor layer from the surface of said fifth semiconductor layer;

an insulating film provided on an inner wall of said trench;

a control electrode provided in said trench to face said fourth semiconductor layer through said insulating film;

a first main electrode provided on the surface of said fourth and fifth semiconductor layers;

a second main electrode provided on the second main surface of said first semiconductor layer; and

wherein a depth of a boundary between said third semiconductor layer and said second semiconductor layer does not exceed a critical value at which a rapid decrease appears in a breakdown voltage of said insulated gate semiconductor device with an increase in said boundary depth.

14. An insulated gate semiconductor device, comprising:

a first semiconductor layer of a first conductivity type having first and second main surfaces;

a second semiconductor layer of a second conductivity type provided over the first main surface of said first semiconductor layer;

a third semiconductor layer of the second conductivity type provided in close contact on a surface of said second semiconductor layer and having an impurity concentration higher than the impurity concentration of said second semiconductor layer;

a fourth semiconductor layer of the first conductivity type provided in close contact on a surface of said third semiconductor layer;

a fifth semiconductor layer of the second conductivity type selectively provided in a surface of said fourth semiconductor layer;

a trench having an opening in a surface of said fifth semiconductor layer and having a trench depth extending through said fourth semiconductor layer into said third semiconductor layer from the surface of said fifth semiconductor layer;

an insulating film provided on an inner wall of said trench;

a control electrode provided in said trench to face said fourth semiconductor layer through said insulating film;

a first main electrode provided on the surface of said fourth and fifth semiconductor layers;

a second main electrode provided on the second main surface of said first semiconductor layer;

an eighth semiconductor layer of the first conductivity type formed to surround a bottom of said trench and having an impurity concentration higher than that in said second semiconductor layer; and

wherein said eighth semiconductor layer is surrounded by said third semiconductor layer.

15. The insulated gate semiconductor device according to claim 14, wherein a depth of a boundary between said third semiconductor layer and said second semiconductor layer does not exceed a critical value at which a rapid decrease appears in a breakdown voltage of said insulated gate semiconductor device with an increase in said boundary depth.