Trenched high breakdown voltage semiconductor device

• US 6,040,600 A
• Filed: 08/11/1997
• Issued: 03/21/2000
• Est. Priority Date: 02/10/1997
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Minato, Tadaharu, Uenishi, Akio
• Primary Examiner(s): Hardy, David B.
• Application Number:
  US08/909,411
• Time in Patent Office: 953 Days
• Field of Search: 257/327-334, 257/347, 257/655
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2252 using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26546 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Abstract

An n type diffusion region and a p type diffusion region are formed in a region sandwiched between trenches arranged at a first main surface of a semiconductor substrate. A p type well is formed in the n- and p-type diffusion regions nearer the first main surface. A source n⁺ diffusion region is formed at the first main surface within the p type well. A gate electrode layer is formed opposite to the p type well sandwiched between the n type diffusion region and the source n⁺ diffusion region with a gate insulating layer disposed therebetween. The n- and p-type diffusion regions each have an impurity concentration distribution diffused from a sidewall surface of a trench. Thus, a fine, micron-order pn repeat structure can be achieved with sufficient precision and a high breakdown voltage semiconductor device is thus obtained which has superior on-state voltage and breakdown voltage as well as fast switching characteristics.

Claims

1. A high breakdown voltage semiconductor device comprising:

a semiconductor substrate having first and second main surfaces opposite to each other and also having a plurality of trenches provided at said first main surface;

a first impurity region of a first conductivity type formed within a region of said semiconductor substrate sandwiched between one and another trenches of said plurality of trenches at a sidewall surface of said one trench;

a second impurity region of a second conductivity type formed within said region sandwiched between said one and another trenches at a sidewall surface of said another trench, and forming a pn junction together with said first impurity region;

a third impurity region of the second conductivity type formed closer to said first main surface than said first and second impurity regions;

a fourth impurity region of the first conductivity type formed on at least one of said first main surface and a sidewall surface of said one trench such that said fourth impurity region is disposed opposite to said first impurity region with said third impurity region disposed therebetween; and

a gate electrode layer opposite to said third impurity region, sandwiched between said first and fourth impurity regions, with a gate insulating layer disposed therebetween;

wherein

said first impurity region has a distribution of concentration of an impurity diffused from a sidewall surface of said one trench; and

said second impurity region has a distribution of concentration of an impurity diffused from a sidewall surface of said another trench.

2. The high breakdown voltage semiconductor device according to claim 1, wherein a source electrode is formed on said first main surface to electrically connect with said third and fourth impurity regions and a drain electrode is formed on said second main surface to electrically connect with said first impurity region.

3. The high breakdown voltage semiconductor device according to claim 1, wherein a source electrode is formed on said first main surface to electrically connect with said third and fourth impurity regions and a drain electrode is formed on said first main surface to electrically connect with said first impurity region.

4. The high breakdown voltage semiconductor device according to claim 1, wherein a space between adjacent said trenches is at most one third of a depth of said trench.

5. The high breakdown voltage semiconductor device according to claim 1, wherein said first impurity region is formed at one of opposing sidewall surfaces of said one trench and an impurity region having a conductivity type different from that of said first impurity region is formed at the other of the opposing sidewall surfaces of said one trench.

6. The high breakdown voltage semiconductor device according to claim 1, wherein said first impurity region is formed at one of opposing sidewall surfaces of said one trench and an impurity region having a same conductivity type as that of said first impurity region is formed on the other of the opposing sidewall surfaces of said one trench.

7. The high breakdown voltage semiconductor device according to claim 1, wherein an inside of said trench is filled with silicon layer having an impurity concentration of at most 10% of an impurity concentration in said first impurity region at a sidewall surface of said one trench.

8. The high breakdown voltage semiconductor device according to claim 2, wherein:

a fifth impurity region of the first conductivity type is formed closer to said second main surface than said first and second impurity regions, said fifth impurity region being higher in impurity concentration than said first impurity region;

said drain electrode is electrically connected to said first impurity region with said fifth impurity region disposed therebetween; and

a silicon layer filling the inside of said trench is spaced apart from said first and second impurity regions by an insulating layer and is also in contact with said fifth impurity region.

9. The high breakdown voltage semiconductor device according to claim 1, wherein an inside of said trench is filled with an insulating layer.

10. The high breakdown voltage semiconductor device according to claim 1, wherein said gate electrode layer extends along a direction in which said one and another trenches extend.

11. The high breakdown voltage semiconductor device according to claim 1, wherein said gate electrode layer extends along a direction in which said gate electrode layer intersects said one and another trenches.

12. The high breakdown voltage semiconductor device according to claim 11, wherein said gate electrode layer has a trench gate structure, is formed at said first main surface, and is arranged only on said first impurity region.

13. The high breakdown voltage semiconductor device according to claim 11, wherein said gate electrode layer has a planer gate structure and is formed on said first main surface.

14. The high breakdown voltage semiconductor device according to claim 2, having a repeat structure in which a pn structure of said first and second impurity regions and said trench are repeated, said pn structure and said trench being adjacent to each other, wherein

a perimeter of said repeat structure is covered with resistive film with a separating insulating layer disposed therebetween, that end portion of said resistive film nearer said first main surface is electrically connected to said source electrode, and that end portion of said resistive film nearer said second main surface is electrically connected to said drain electrode.

15. The high breakdown voltage semiconductor device according to claim 2, having a repeat structure in which a pn structure of said first and second impurity regions and said trench are repeated, said pn structure and said trench being adjacent to each other, wherein

a perimeter of said repeat structure is connected to a semiconductor region of the first conductivity type, and a tip of a depletion layer extending from said repeat structure when voltage is applied to said drain electrode ends within said semiconductor region.

16. The high breakdown voltage semiconductor device according to claim 15, wherein:

a diffusion length of an impurity of said first impurity region from a sidewall surface of said one trench is shorter than a width of said first impurity region between the sidewall surface of said one trench and said pn junction of said first and second impurity regions; and

a diffusion length of an impurity of said second impurity region from a sidewall surface of said another trench is shorter than a width of said second impurity region between the sidewall surface of said another trench and said pn junction of said first and second impurity regions.

17. The high breakdown voltage semiconductor device according to claim 15, having a repeat structure in which a pn structure of said first and second impurity regions and said trench are repeated, said pn structure and said trench being adjacent to each other, wherein

a space between said trenches is narrower at a perimeter than a center of said repeat structure at said first main surface.

18. The high breakdown voltage semiconductor device according to claim 15, wherein a filling layer including silicon as a material fills an inside of said trench and an impurity concentration of said filling layer is lower than that of said semiconductor region.

19. The high breakdown voltage semiconductor device according to claim 15, wherein a total amount of an impurity which is opposite in conductivity to said semiconductor region is larger when a total amount of an impurity of the first conductivity type introduced into said first and second impurity regions is compared with that of an impurity of the second conductivity type introduced into said first and second impurity region.

20. A high breakdown voltage semiconductor device comprising:

an SOI semiconductor substrate having first and second main surfaces opposite to each other, said SOI semiconductor substrate having a substrate arranged nearer said second main surface and a semiconductor layer arranged nearer said first main surface and insulated from said substrate, and also having a plurality of trenches provided at said first main surface;

a first impurity region of a first conductivity type formed within a region of said semiconductor layer sandwiched between one and another trenches of said plurality of trenches at a sidewall surface of said one trench;

a second impurity region of a second conductivity type formed within said region sandwiched between said one and another trenches at a sidewall surface of said another trench, and forming a pn junction together with said first impurity region;

a third impurity region of the second conductivity type formed within said semiconductor layer;

a fourth impurity region of the first conductivity type formed on at least one of said first main surface and a sidewall surface of said one trench such that said fourth impurity region is disposed opposite to said first impurity region with said third impurity region disposed therebetween; and

a gate electrode layer opposite to said third impurity region, sandwiched between said first and fourth impurity regions, with a gate insulating layer disposed therebetween;

wherein

said first impurity region has a distribution of concentration of an impurity diffused from a sidewall surface of said one trench; and

said second impurity region has a distribution of concentration of an impurity diffused from a sidewall surface of said another trench;

a source electrode formed on said first main surface electrically connected with said third and fourth impurity regions and

a drain electrode formed on said first main surface electrically connected with said first impurity region.