Semiconductor component comprising an electrostatic-discharge protection device

• US 6,040,604 A
• Filed: 07/21/1997
• Issued: 03/21/2000
• Est. Priority Date: 07/21/1997
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lauvray, Olivier J., Rodriguez, David
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): EATON, KURT M
• Application Number:
  US08/897,964
• Time in Patent Office: 974 Days
• Field of Search: 438/652, 438/597, 438/622, 438/598, 438/618, 438/637, 438/638, 438/666, 438/669, 438/280, 438/514, 438/527, 438/533, 257/776, 257/758, 257/328, 257/355, 257/740, 257/774
• US Class Current: 257/355
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor component (10) includes a substrate (11), doped regions (15, 20) in the substrate (11), interconnect layers (23, 26, 29) coupled to one of the doped layers, and dielectric layers (21, 24, 27) between the interconnect layers (23, 26, 29) wherein a portion (48) of the top interconnect layer (29) overlies portions (47, 42, 43) of the underlying interconnect layers (23, 26) and wherein a portion (47) of the middle interconnect layer (26) does not overlie the portions (42, 43) of the bottom interconnect layer (23) and also does not overlie portions (32, 33) of one of the doped regions (20).

Claims

1. A semiconductor component comprising:

a substrate;

a first doped region in the substrate;

an electrostatic-discharge protection device in the substrate comprising a second doped region in the substrate wherein a first portion of the second doped region contacts the first doped region at a first portion of the substrate;

a first interconnect layer overlying the electrostatic-discharge protection device, wherein a ring-shaped portion of the first interconnect layer overlies and contacts a second portion of the second doped region;

a second interconnect layer overlying the first interconnect layer and the electrostatic-discharge protection device, wherein a portion of the second interconnect layer overlies and contacts the first interconnect layer, overlies the electrostatic-discharge protection device, is devoid of overlying the ring-shaped portion of the first interconnect layer, and is devoid of overlying the first and second portions of the second doped region; and

a third interconnect layer overlying the first and second interconnect layers and the electrostatic-discharge protection device, wherein a portion of the third interconnect layer overlies and contacts the second interconnect layer, overlies the electrostatic-discharge protection device, and overlies the portions of the first and second interconnect layers.

2. The semiconductor component of claim 1 wherein the portions of the first and third interconnect layers are devoid of overlying the first doped region.

3. The semiconductor component of claim 1 wherein the portion of the third interconnect layer overlies the first doped region, and

wherein the ring-shaped portion of the first interconnect layer is devoid of overlying the first doped region.

4. The semiconductor component of claim 1 wherein the portions of the first and third interconnect layers overlie the first doped region.

5. The semiconductor component of claim 1 wherein the portion of the third interconnect layer is larger than the portion of the second interconnect layer.

6. A semiconductor component comprising:

a semiconductor substrate having a first conductivity type and a first doping concentration;

a first doped region in the semiconductor substrate, the first doped region having a second conductivity type and separating the semiconductor substrate into first and second portions;

a semiconductor device in the first portion of the semiconductor substrate;

an electrostatic-discharge protection device in the second portion of the semiconductor substrate comprising a second doped region in a first area of the second portion of the semiconductor substrate, the second doped region having the first conductivity type and a second doping concentration greater than the first doping concentration, wherein a first portion of the second doped region contacts the first doped region at a second area of the second portion of the semiconductor substrate;

a first dielectric layer over the semiconductor substrate and the electrostatic-discharge protection device, the first dielectric layer having a ring-shaped via exposing the second doped region, the via of the first dielectric layer overlying the electrostatic-discharge protection device;

an interconnect layer over the first dielectric layer and in the ring-shaped via of the first dielectric layer to contact the second doped region;

a second dielectric layer over the interconnect layer, the semiconductor substrate, and the electrostatic-discharge protection device, the second dielectric layer having a via not overlying the ring-shaped via and exposing the interconnect layer, the via in the second dielectric layer overlying the electrostatic-discharge protection device and devoid of overlying the ring-shaped via in the first dielectric layer and the first portion of the second doped region;

a metal layer over the second dielectric layer and in the via of the second dielectric layer to contact the interconnect layer;

a third dielectric layer over the metal layer, the semiconductor substrate, and the electrostatic-discharge protection device, the third dielectric layer having a via exposing the metal layer, the via in the third dielectric layer overlying the vias in the first and second dielectric layers and the electrostatic-discharge protection device, the via in the third dielectric layer larger than the vias in the first and second dielectric layers; and

a wire bond in the via of the third dielectric layer to contact the metal layer.

7. The semiconductor component of claim 6 wherein the vias in the first and third dielectric layers are devoid of overlying the first portion of the second doped region.

8. The semiconductor component of claim 6 wherein the ring-shaped via in the first dielectric layer is devoid of overlying the first portion of the second doped region, and wherein the via in the third dielectric layer overlies the first portion of the second doped region.

9. The semiconductor component of claim 6 wherein the vias in the first and third dielectric layers overlie the first portion of the second doped region.