Multi-chip module employing a carrier substrate with micromachined alignment structures and method of forming

• US 6,040,618 A
• Filed: 03/06/1997
• Issued: 03/21/2000
• Est. Priority Date: 03/06/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Cao, Phat X.
• Application Number:
  US08/812,476
• Time in Patent Office: 1,111 Days
• Field of Search: 257/586, 257/622, 257/623, 257/778, 257/779, 257/737, 257/738, 257/618
• US Class Current: 257/586
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/10165 Alignment aids
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A micromachined insulative carrier substrate preferably formed of silicon and a multi-chip module formed from the micromachined substrate. The micromachined substrate is fabricated by forming mesas across the surface of the substrate, forming an insulating layer on the substrate, and forming conductive traces on the insulating layer to route signals between semiconductor dice and/or to external circuitry. A variety of semiconductor dice and/or integrated circuitry-bearing wafer configurations (collectively, "semiconductor elements") may be attached to the semiconductor substrate. Electrical contact between the carrier substrate and semiconductor element is achieved with conductive connectors formed on either the semiconductor element or the carrier substrate. The conductive connectors each preferably make contact with both a portion of the conductive trace extending down the sidewall of the mesa and a portion of the conductive trace on the substrate between the mesas to form a more effective bond. The present invention also includes a stacked configuration. After attachment of semiconductor elements, the carrier substrates can be stacked to form a high density stacked configuration.

Claims

1. A carrier substrate for a semiconductor element, comprising:

a substrate with a substantially planar surface having at least one elongated, substantially linear mesa defined by two inclined sidewalls rising therefrom and extending to a top surface substantially parallel to said substantially planar surface;

an insulating layer disposed over said substantially planar substrate surface and said at least one elongated substantially linear mesa; and

a plurality of conductive traces extending over said insulating layer and including mutually parallel, laterally spaced, substantially linear segments oriented transversely to said at least one elongated, substantially linear mesa, said mutually parallel, laterally spaced, substantially linear segments of said plurality of conductive traces each extending over a first portion of said planar substrate surface on one side of said at least one elongated mesa, over said at least one elongated, substantially linear mesa and onto a second portion of said substantially planar substrate surface on an opposing side of said at least one elongated, substantially linear mesa.

2. The carrier substrate of claim 1, wherein said substrate is selected from a group consisting of monocrystalline silicon, silicon-on-glass, silicon-on-sapphire, germanium, and ceramic.

3. The carrier substrate of claim 1, wherein said insulating layer includes silicon dioxide.

4. The carrier substrate of claim 1, wherein said plurality of conductive traces includes copper.

5. The carrier substrate of claim 4, wherein said plurality of conductive traces further comprises a layer of chrome on said insulating layer, a layer of copper/chrome alloy on said chrome layer, and a layer of copper on said copper/chrome alloy layer.

6. The carrier substrate of claim 1, further comprising a passivation layer over said insulating layer and said plurality of conductive traces, said passivation layer including apertures therethrough exposing contact areas at predetermined locations on said plurality of conductive traces.

7. The carrier substrate of claim 1, wherein said at least one elongated mesa comprises a plurality of substantially parallel elongated mesas of similar length, and at least one of said plurality of conductive traces extends into an area between at least two of said plurality of substantially parallel elongated mesas after passing over at least one of said at least one elongated mesa.

8. The carrier substrate of claim 1, wherein said at least one elongated, substantially linear mesa comprises four elongated, substantially linear mesas substantially defining a rectangle bounding a substantially enclosed area into which said plurality of conductive traces extends after passing over at least one of said four elongated, substantially linear mesas.

9. The carrier substrate of claim 1, wherein said at least one elongated, substantially linear mesa comprises two substantially parallel, elongated, substantially linear mesas, and said plurality of conductive traces comprises two groups of traces, each of said two groups comprising a plurality of traces, each group of traces extending over a different one of said two substantially parallel, elongated, substantially linear mesas from a location remote from an area between said two substantially parallel, elongated, substantially linear mesas and terminating at a location on said substantially planar substrate element between said two substantially parallel, elongated, substantially linear mesas.

10. The carrier substrate of claim 9, wherein each trace of at least one of said two groups terminates between said two substantially parallel, elongated, substantially linear mesa along a common boundary parallel to the elongated, substantially linear mesa over which said plurality of traces of said at least one of said two groups extend.

11. The carrier substrate of claim 9, wherein at least some traces of said plurality of traces extend substantially to a peripheral edge of said substrate.

12. The carrier substrate of claim 1, further comprising a passivation layer covering said plurality of conductive traces and having apertures therethrough exposing portions of said plurality of conductive traces lying over said substantially planar substrate surface on said opposing side of said at least one elongated, substantially linear mesa and over a sidewall of said at least one elongated, substantially linear sidewall adjacent thereto.

13. The carrier substrate of claim 1, wherein said at least one elongated mesa comprises two mutually parallel elongated mesas, and at least one of said plurality of conductive traces extends from a location outside said two mutually parallel elongated mesas and over one of said two mutually parallel elongated mesas to an area between said two mutually parallel elongated mesas and at least partially up a sidewall of the second of said two mutually parallel elongated mesas.

14. The carrier substrate of claim 13, wherein said two mutually parallel elongated mesas are spaced apart by a distance substantially corresponding to a lateral dimension of conductive connectors of a flip-chip semiconductor element to be carried by said carrier substrate so that at least one of said conductive connectors will contact said at least one of said plurality of conductive traces over a sidewall of each of said two mutually parallel elongated mesas and over said substantially planar substrate surface therebetween.

15. The carrier substrate of claim 1, further comprising a layer of reflowable material disposed on said plurality of conductive traces at a location over said substantially planar substrate surface on said opposing side of said at least one elongated, substantially linear mesa and over an adjacent sidewall thereof.

16. The carrier substrate of claim 15, wherein said reflowable material comprises a solder material comprised substantially of tin and lead.

17. The carrier substrate of claim 1, wherein said substrate possesses a CTE substantially the same as that of a flip-chip configured semiconductor element to be carried thereon.

18. A semiconductor device, comprising:

a carrier substrate with a substantially planar surface having at least one elongated mesa defined by inclined sidewalls rising therefrom to a top substantially parallel to said substantially planar surface;

an insulating layer disposed over said substantially planar substrate surface and said at least one elongated mesa;

a plurality of conductive traces extending over said insulating layer and including mutually parallel, laterally spaced segments oriented transversely to said at least one elongated mesa, said plurality of mutually parallel, laterally spaced segments of said conductive traces each extending over a first portion of said substantially planar substrate surface on one side of said at least one elongated mesa, over said at least one elongated mesa and onto a second portion of said substantially planar substrate surface on an opposing side of said at least one elongated mesa; and

at least one semiconductor element having an active surface including a plurality of conductive connectors projecting transversely therefrom, each conductive connector of said plurality being in electrical contact with one of said plurality of conductive trace segments on a first area thereof located over a sidewall of said at least one elongated mesa and a second area thereof adjacent said first area and located over said substantially planar substrate surface.

19. The semiconductor device of claim 18, wherein said carrier substrate is selected from a group consisting of monocrystalline silicon, silicon-on-glass, silicon-on-sapphire, germanium, and ceramic.

20. The semiconductor device of claim 18, wherein said insulating layer includes silicon dioxide.

21. The semiconductor device of claim 18, wherein said plurality of conductive traces includes copper.

22. The semiconductor device of claim 21, wherein said plurality of conductive traces further comprises a layer of chrome on said insulating layer, a layer of copper/chrome alloy on said chrome layer, and a layer of copper on said copper/chrome alloy layer.

23. The semiconductor device of claim 18, further comprising a passivation layer over said insulating layer and said plurality of conductive traces, said passivation layer including apertures therethrough exposing contact areas over predetermined locations on said plurality of conductive traces.

24. The semiconductor device of claim 18, wherein said at least one semiconductor element includes a semiconductor chip.

25. The semiconductor device of claim 18, wherein said carrier substrate and said at least one semiconductor element each comprise an entire silicon wafer.

26. The semiconductor device of claim 18, wherein said at least one elongated mesa comprises at least two mutually parallel, adjacent elongated mesas, and further comprising at least one conductive trace extending down a sidewall of one of said at least two elongated mesas, onto said substantially planar substrate surface, and up a sidewall of another of said at least two elongated mesas;

and wherein said at least one conductive connector of said plurality of conductive connectors is received between said one and said another of said at least two elongated mesas and electrically contacts said at least one conductive trace over said sidewall of said one of said at least two elongated mesas, over said substantially planar substrate surface, and over said sidewall of said another of said at least two elongated mesas.

27. The semiconductor device of claim 18, wherein said conductive connectors comprise balls of reflowable material.

28. The semiconductor device of claim 27, wherein said balls comprise a lead/tin alloy.

29. The semiconductor device of claim 18, wherein said at least some of said plurality of traces lying over said sidewall of said at least one elongated mesa are at least partially covered with a reflowable material compatible with a material of said plurality of conductive connectors.

30. The semiconductor device of claim 29, wherein said conductive connectors are comprised of a tin/lead composition having a first melting point, and said reflowable material comprises a tin/lead composition having a second, lower melting point.

31. The semiconductor device of claim 18, wherein said conductive connectors are comprised of a reflowable material.

32. The semiconductor device of claim 31, wherein said reflowable material comprises a tin/lead composition.

33. The semiconductor device of claim 18, wherein said conductive connectors comprise an epoxy.

34. The semiconductor device of claim 18, wherein said conductive connectors comprise a thermoplastic.

35. The semiconductor device of claim 18, wherein said plurality of conductive traces is substantially covered with a passivation layer in an area between said at least one semiconductor element and said carrier substrate, with the exception of areas of contact between said conductive connectors and said plurality of conductive traces.