Multi-chip module employing a carrier substrate with micromachined alignment structures and method of forming
First Claim
1. A carrier substrate for a semiconductor element, comprising:
- a substrate with a substantially planar surface having at least one elongated, substantially linear mesa defined by two inclined sidewalls rising therefrom and extending to a top surface substantially parallel to said substantially planar surface;
an insulating layer disposed over said substantially planar substrate surface and said at least one elongated substantially linear mesa; and
a plurality of conductive traces extending over said insulating layer and including mutually parallel, laterally spaced, substantially linear segments oriented transversely to said at least one elongated, substantially linear mesa, said mutually parallel, laterally spaced, substantially linear segments of said plurality of conductive traces each extending over a first portion of said planar substrate surface on one side of said at least one elongated mesa, over said at least one elongated, substantially linear mesa and onto a second portion of said substantially planar substrate surface on an opposing side of said at least one elongated, substantially linear mesa.
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Accused Products
Abstract
A micromachined insulative carrier substrate preferably formed of silicon and a multi-chip module formed from the micromachined substrate. The micromachined substrate is fabricated by forming mesas across the surface of the substrate, forming an insulating layer on the substrate, and forming conductive traces on the insulating layer to route signals between semiconductor dice and/or to external circuitry. A variety of semiconductor dice and/or integrated circuitry-bearing wafer configurations (collectively, "semiconductor elements") may be attached to the semiconductor substrate. Electrical contact between the carrier substrate and semiconductor element is achieved with conductive connectors formed on either the semiconductor element or the carrier substrate. The conductive connectors each preferably make contact with both a portion of the conductive trace extending down the sidewall of the mesa and a portion of the conductive trace on the substrate between the mesas to form a more effective bond. The present invention also includes a stacked configuration. After attachment of semiconductor elements, the carrier substrates can be stacked to form a high density stacked configuration.
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Citations
35 Claims
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1. A carrier substrate for a semiconductor element, comprising:
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a substrate with a substantially planar surface having at least one elongated, substantially linear mesa defined by two inclined sidewalls rising therefrom and extending to a top surface substantially parallel to said substantially planar surface; an insulating layer disposed over said substantially planar substrate surface and said at least one elongated substantially linear mesa; and a plurality of conductive traces extending over said insulating layer and including mutually parallel, laterally spaced, substantially linear segments oriented transversely to said at least one elongated, substantially linear mesa, said mutually parallel, laterally spaced, substantially linear segments of said plurality of conductive traces each extending over a first portion of said planar substrate surface on one side of said at least one elongated mesa, over said at least one elongated, substantially linear mesa and onto a second portion of said substantially planar substrate surface on an opposing side of said at least one elongated, substantially linear mesa. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A semiconductor device, comprising:
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a carrier substrate with a substantially planar surface having at least one elongated mesa defined by inclined sidewalls rising therefrom to a top substantially parallel to said substantially planar surface; an insulating layer disposed over said substantially planar substrate surface and said at least one elongated mesa; a plurality of conductive traces extending over said insulating layer and including mutually parallel, laterally spaced segments oriented transversely to said at least one elongated mesa, said plurality of mutually parallel, laterally spaced segments of said conductive traces each extending over a first portion of said substantially planar substrate surface on one side of said at least one elongated mesa, over said at least one elongated mesa and onto a second portion of said substantially planar substrate surface on an opposing side of said at least one elongated mesa; and at least one semiconductor element having an active surface including a plurality of conductive connectors projecting transversely therefrom, each conductive connector of said plurality being in electrical contact with one of said plurality of conductive trace segments on a first area thereof located over a sidewall of said at least one elongated mesa and a second area thereof adjacent said first area and located over said substantially planar substrate surface. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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Specification