Test head for integrated circuit tester arranging tester component circuit boards on three dimensions

• US 6,040,691 A
• Filed: 05/23/1997
• Issued: 03/21/2000
• Est. Priority Date: 05/23/1997
• Status: Expired due to Fees

• Current Assignee: Credence Systems Corporation (COHU Incorporated)
• Original Assignee: Credence Systems Corporation (COHU Incorporated)
• Inventors: Stanford, Dean, Miller, Charles A., Hanners, John C.
• Primary Examiner(s): Ballato, Josie
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US08/862,596
• Time in Patent Office: 1,033 Days
• Field of Search: 324/158.1, 324/754, 324/755, 324/757, 324/758, 324/765
• US Class Current: 324/756.07
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/2891 related to sensing or controlling of force, position, temperature G01R31/2874 takes precedence; sensing of force G01L; sensing of position G01B, G01D; sensing of temperature G01K; controlling in general G05
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture

Abstract

A test head for an integrated circuit tester includes a horizontal base holding a motherboard. The motherboard distributes test instructions to an array of daughterboards mounted thereon, the daughterboards being radially distributed about a central vertical axis of the motherboard. Each daughterboard holds a set of node cards and includes data paths for forwarding the test instructions from the motherboard to the node cards. Each node card contains circuits for transmitting test signals to and receiving response signals from a separate terminal of a device under test (DUT) in response to the test instructions forwarded thereto. Edges of the daughterboards extend downward through apertures in the base to contact pads on an interface board holding the DUT. The daughterboards provide conductive paths for the test and response signals extending between the node cards and pads on the DUT interface board. The interface board extends those conductive paths from the pads to terminals of the DUT.

Claims

1. A test head for an electronic circuit tester of the type having a plurality of tester nodes, each tester node communicating with a device under test (DUT) during a test via a separate test signal, the test head comprising:

a plurality of node cards, each having a first planar surface holding at least one of said tester nodes;

a plurality of daughterboards, each having connectors on a second planar surface holding a plurality of said node cards;

a DUT interface board for holding said DUT, said DUT interface board having a third planar surface containing a plurality of contact pads and having means for conveying test signals between said DUT and said contact pads; and

means for holding said daughterboards such that each daughterboard contacts a separate subset of said contact pads and such that their second planar surfaces lie in separate planes intersecting at a single common axis perpendicular to said third planar surface of said DUT interface board.

2. The test head in accordance with claim 1 wherein each daughterboard includes means for conveying test signals between the contact pads it contacts and the node cards it holds.

3. The test head in accordance with claim 1 wherein the second planar surface of each daughterboard holds the first planar surface of at least one of said node cards parallel to said third planar surface of said DUT interface board.

4. The test head in accordance with claim 3 wherein each daughterboard also holds the first planar surface of at least one other of said node cards other than parallel to said third planar surface of said DUT interface board.

5. The test head in accordance with claim 1 wherein said node cards form a three-dimensional array.

6. The test head in accordance with claim 1 wherein said means for holding holds each daughterboard such that its second planar surface is perpendicular to said third planar surface of said DUT interface board.

7. The test head in accordance with claim 1 wherein said node cards each have a narrow end positioned nearest said vertical axis and a wider end positioned farthest from said vertical axis.

8. The test head in accordance with claim 1 wherein said means for holding holds said daughterboards such that their second planar surfaces lie in planes perpendicular to said third planar surface of said DUT interface board, each of said planes intersecting and such that said second planar surfaces form a substantially circular array about said axis.

9. The test head in accordance with claim 8 wherein the second planar surfaces of adjacent pairs of said daughter boards substantially face one another.

10. The test head in accordance with claim 9 wherein at least a portion of the node cards held by a first daughterboard of an adjacent pair of said daughterboards are spatially interleaved with node cards held by a second daughterboard of said adjacent pair.

11. The test head in accordance with claim 8 including structural members affixed to and extending between adjacent pairs of said daughterboards.

12. The test head in accordance with claim 1 wherein said means for holding said daughterboards such that each daughterboard contacts a separate subset of said contact pads, comprises:

a base plate having parallel fourth and fifth planar surfaces, said third planar surface of said DUT interface board being adjacent to said fourth planar surface, said base plate having at least one aperture extending through said fourth and fifth planar surfaces; and

a motherboard mounted on said fifth planar surface of said base plate and containing connectors for holding said daughterboards,

wherein a portion of each daughterboard, when held by one of said connectors, extends through said at least one aperture in said base plate and contacts said subset of said contact pads.

13. The test head in accordance with claim 12 further comprising:

a support member having an outer surface and extending from said fifth planar surface of said base plate, and

a plurality of card holders mounted on said outer surface of said support member for receiving and holding said daughterboards.

14. The test head in accordance with claim 13 wherein said support member is substantially cylindrical in shape.

15. The test head in accordance with claim 13 further comprising:

an air pump, and

means for attaching said air pump to said support member such that said air pump pumps air from an interior of said support member.

16. The test head in accordance with claim 15 wherein said outer surface of said support member is slotted such that when said air pump pumps air from the interior of said support member, air enters said interior through the slotted surface.

17. The test head in accordance with claim 16 further comprising a slotted cover attached to said base plate and covering said daughterboards.

18. A test head for an electronic circuit tester of the type having a plurality of tester nodes, each tester node communicating with a device under test (DUT) during a test via a separate test signal in response to an input set of instructions, the test head comprising:

a plurality of node cards, each having a first planar surface holding at least one of said tester nodes;

a plurality of daughterboards, each having a second planar surface holding a plurality of said node cards;

a DUT interface board for holding said DUT, said DUT interface board having a third planar surface containing a plurality of contact pads and having means for conveying test signals between said DUT and said contact pads; and

a base plate having parallel fourth and fifth planar surfaces, said third planar surface of said DUT interface board being adjacent to said fourth planar surface, said base plate having at least one aperture extending through said fourth and fifth planar surfaces; and

a motherboard mounted on said fifth planar surface of said base plate, said motherboard holding said daughterboards, wherein a portion of each daughterboard extends through said at least one aperture in said base plate and contacts ones of said contact pads, and wherein said motherboard includes means for receiving said input instructions and distributing them to said daughterboards, and wherein each daughterboard includes means for receiving said input instructions from said motherboard and for distributing them to the node cards it holds.

19. The test head in accordance with claim 18 wherein said motherboard comprises:

a plurality of motherboard sections mounted on said base plate, and

a plurality of motherboard connectors linking said motherboard sections, said connectors conveying said input instructions between said motherboard sections.

20. The test head in accordance with claim 18 further comprising a set of power conversion circuits each for producing at least one output power signal in response to an input power signal,

wherein the input and output power signals have differing voltage levels, each daughterboard holding at least one of said power conversion circuits, and

wherein each daughterboard includes means for conveying said at least one output power signal to the node cards mounted thereon.

21. The test head in accordance with claim 20

wherein said motherboard includes means for delivering said input power signal to each of said daughterboards,

wherein each of said daughterboards includes means for delivering said input power signal from said motherboard to the power conversion circuit mounted thereon.

22. The test head in accordance with claim 18 wherein each daughterboard includes a back planar surface parallel to said second planar surface for holding at least one of said power conversion circuits and includes a ground plane between said second planar surface and said back planar surface.

23. A test head for an integrated circuit tester, for responding to input instructions by testing an integrated circuit device under test (DUT) having a plurality of terminals, the apparatus comprising:

a horizontal base plate having a plurality of apertures distributed about a vertical axis;

an interface board positioned below said base plate for holding said DUT and having a plurality of conductors below said apertures for contacting said terminals of said DUT;

a plurality of node cards each containing a tester node for transmitting and receiving test signals in response to the test instructions supplied as input thereto;

a substantially planar motherboard mounted above said base plate; and

a plurality of substantially planar daughterboards mounted on said motherboard in vertical planes radially arrayed about said central vertical axis, each daughterboard holding a separate subset of said node cards, each daughterboard having an edge extending downward through one of said apertures in said base and contacting one of said conductors on said interface, the daughterboards including conductive paths for the test signals extending between the node cards and said conductors on the DUT interface board.

24. The test head in accordance with claim 23

wherein the motherboard includes means for receiving said input test instructions and distributing them to said daughterboards, and

wherein said daughterboards include means for forwarding the test instructions from the motherboard to the node cards.

25. The test head in accordance with claim 23 wherein each of said node cards comprises:

a first surface;

a second surface parallel to said first surface;

a ground plane between said first and second surfaces;

said tester node mounted on said first surface; and

a power conversion circuit mounted on said second surface for producing at least one output power signal for said tester node in response to an input power signal, wherein the input power signal and the output power signal have differing voltage levels.

26. The test head in accordance with claim 23 wherein adjacent pairs of daughterboards hold their node cards therebetween.

27. The test head in accordance with claim 26 further comprising structure members affixed to and extending between adjacent pairs of daughterboards.

28. The test head in accordance with claim 23 wherein said node cards each have a narrow end positioned nearest said vertical axis and a wider end positioned farthest from said vertical axis.

29. A test head for an integrated circuit tester, the integrated circuit tester being of the type having a plurality of tester nodes, each tester node comprising an electronic circuit for communicating with a separate terminal of an integrated circuit device under test (DUT) while the tester is testing the DUT, the test head comprising:

a motherboard disposed in a horizontal plane and having a plurality of apertures therein;

a DUT interface board for holding said DUT, the DUT interface having a surface held in a horizontal plane below said motherboard, a plurality of contact pads distributed on said surface below said apertures, and means for conveying signals between said contact pads and terminals of said DUT,

a plurality of node cards, each containing at least one of said tester nodes;

a plurality of daughterboards, held on said motherboard in vertical planes radially disposed about a vertical axis passing through the motherboard, each daughterboard holding a plurality of said node cards, each daughterboard including conductive means, each extending through one of said apertures in said motherboard and contacting a separate contact pad of said DUT interface board for conveying a signal from said contact pad to one of said node cards.

30. The test head in accordance with claim 29 wherein said node cards are arranged on said daughterboards such that some of said plurality of node cards are substantially above others of said plurality of node cards.

31. The test head in accordance with claim 29 wherein said conductive means comprises a pogo pin assembly mounted on a lower edge of said daughterboard.

32. The test head in accordance with claim 29 further comprising:

a cylindrical support member having an interior and having a slotted surface extending upward from said motherboard about said vertical axis,

a plurality of card connectors mounted on said outer surface of said cylindrical support member for receiving and holding said daughterboards,

an air pump, and

means for attaching said air pump to said cylindrical support member such that said air pump pumps air from an interior of said cylindrical support member and such that air enters said interior through the slotted surface.

33. The test head in accordance with claim 32 further comprising a slotted cover surrounding said daughterboards.

34. The test head in accordance with claim 29 wherein each of said node cards comprises:

said node electronics;

a first surface for holding said node electronics;

a second surface for holding power conversion circuits for producing at least one output power signal in response to an input power signal, wherein the input power signal and the output power signal have differing voltage levels;

a ground plane between and substantially coextensive with said first an second surfaces;

means for delivering said output power signal to said node electronics,

wherein said node cards are oriented on said daughterboards such that the first surface of each node card substantially faces the first surface of a first adjacent node card, if any, and the second surface of each node card substantially faces the second surface of a second adjacent node card, if any, and

wherein said daughterboards include opposing front and back surfaces, the node card connectors being mounted on said front surface and a ground plane covering said second surface.

35. The test head in accordance with claim 34 wherein said node cards have a narrow end positioned nearest said vertical axis and a wide end positioned farthest from said vertical axis.