CML-CMOS conversion circuit

• US 6,040,710 A
• Filed: 06/04/1998
• Issued: 03/21/2000
• Est. Priority Date: 06/05/1997
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Nakauchi, Osamu
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/092,012
• Time in Patent Office: 656 Days
• Field of Search: 326/66, 326/64, 326/73, 326/77, 326/63, 326/84, 326/110, 326/127, 326/126, 326/67, 326/74
• US Class Current: 326/66
• CPC Class Codes: H03K 19/017527 with at least one differential stage

Abstract

A CML-CMOS conversion circuit according to this invention includes: a differential circuit in which resistance is connected as load; a first current mirror circuit made up from an n-channel MOS transistor connected to one output of the differential circuit; a second current mirror circuit made up from an n-channel MOS transistor connected to the other output of the differential circuit; a third current mirror circuit made up of two p-channel MOS transistors connected in series to the first current mirror circuit and the second current mirror circuit; and a CMOS inverter that takes as input the output signal of the second current mirror circuit and that outputs a signal at CMOS logic amplitude.

Claims

1. A CML-CMOS conversion circuit that converts input signals complementary-inputted at CML (Current Mode Logic) amplitude into signals of CMOS (Complementary Metal Oxide Semiconductor) logic amplitude and outputs a result, comprising:

a differential circuit that is connected to resistors that function as load and that amplifies and complementary-outputs a difference in potential between a positive input signal, which is one signal of said input signals, and an inverted input signal, which is another signal of said input signals;

a first current mirror circuit that is connected to one output of said differential circuit;

a second current mirror circuit that is connected to the other output of said differential circuit;

a third current mirror circuit that is provided with a first transistor connected in a series to the output of said first current mirror circuit and a second transistor connected in a series with the output of said second current mirror circuit, wherein said second transistor enters a conductive state when current flows to said first transistor and said second transistor enters a nonconductive state when current does not flow to said first transistor; and

a CMOS inverter that is provided with a p-channel MOS transistor and a first n-channel MOS transistor that are in complementary connection, that takes as input a signal outputted from said second current mirror circuit, and that outputs a signal at CMOS logic amplitude.

2. The CML-CMOS conversion circuit according to claim 1 wherein said differential circuit comprises:

a first bipolar transistor into which said positive input signals are inputted, and having a first resistor is connected as load between the collector and the power supply terminal; and

a second bipolar transistor into which said inverted input signals are inputted, and having its emitter connected in common with the emitter of said first bipolar transistor and a second resistor is connected as load between the collector and the power supply terminal.

3. The CML-CMOS conversion circuit according to claim 1 wherein said first current mirror circuit is provided with:

a second n-channel MOS transistor connected to one output of said differential circuit; and

a third n-channel MOS transistor having its gate connected in common with the gate of said second n-channel MOS transistor;

wherein said third n-channel MOS transistor enters a conductive state when current flows to said second n-channel MOS transistor, and said third n-channel MOS transistor enters a nonconductive state when current does not flow to said second n-channel MOS transistor.

4. The CML-CMOS conversion circuit according to claim 1 wherein said second current mirror circuit is provided with:

a second n-channel MOS transistor connected to the other output of said differential circuit; and

a third n-channel MOS transistor having its gate connected in common with the gate of said second n-channel MOS transistor;

wherein said third n-channel MOS transistor enters a conductive state when current flows to said second n-channel MOS transistor, and said third n-channel MOS transistor enters a nonconductive state when current does not flow to said second n-channel MOS transistor.

5. The CML-CMOS conversion circuit according to claim 1 wherein said first transistor and said second transistor are each p-channel MOS transistors.

6. The CML-CMOS conversion circuit according to claim 2 wherein:

the resistance of said first resistor is set such that the output voltage of the collector of said first bipolar transistor is 0.4 V or less when said first bipolar transistor is in an conductive state; and

the resistance of said second resistor is set such that the output voltage of the collector of said second bipolar transistor is 0.4 V or less when said second bipolar transistor is in a conductive state.