Method for programming an analog/multi-level flash EEPROM
First Claim
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1. A method for programming a multi-level floating gate memory cell, comprising the steps of:
- searching a program data-line voltage of the cell and ascertaining that said program data-line voltage is less than a first program verification margin for each data-line of the cell by using a first number of program pulse shots having a first pulse width and a second number of program pulse shots having a second pulse width and recording the program data-line voltage of the cell;
using the recorded program data-line voltage for each bit-line and page programming the cell using a third number of program pulse shots having a third pulse width until the cell has less than a second program verification margin;
determining whether the cell is programmed within the second program verification margin; and
if notiteratively applying another program retry pulse to the cell and determining whether the cell is programmed, until the cell is programmed within the second program verification margin or a maximum number, M, of retries is made;
using the recorded data-line voltage for each bit-line and page programming the cell using a fourth number of program pulses having a fourth pulse width until the cell has less than a third program verification margin;
determining whether the cell is programmed within the third program verification margin; and
if notiteratively applying another program retry pulse to the cell and determining whether the cell is programmed, until the cell is programmed within the third program verification margin or a maximum number, N, of retries is made.
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Abstract
A method for programming an analog/multi-level flash memory array, which insures fast programming to substantially all of the cells in the array, without over-programming, is based on providing a pattern of program retry pulses which have respective pulse widths and pulse heights which vary according to a pattern. The pattern includes three stages which program and verify cell threshold voltages with different program verification margins so that an accurate cell threshold voltage can be achieved for each cell.
153 Citations
33 Claims
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1. A method for programming a multi-level floating gate memory cell, comprising the steps of:
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searching a program data-line voltage of the cell and ascertaining that said program data-line voltage is less than a first program verification margin for each data-line of the cell by using a first number of program pulse shots having a first pulse width and a second number of program pulse shots having a second pulse width and recording the program data-line voltage of the cell; using the recorded program data-line voltage for each bit-line and page programming the cell using a third number of program pulse shots having a third pulse width until the cell has less than a second program verification margin; determining whether the cell is programmed within the second program verification margin; and
if notiteratively applying another program retry pulse to the cell and determining whether the cell is programmed, until the cell is programmed within the second program verification margin or a maximum number, M, of retries is made; using the recorded data-line voltage for each bit-line and page programming the cell using a fourth number of program pulses having a fourth pulse width until the cell has less than a third program verification margin; determining whether the cell is programmed within the third program verification margin; and
if notiteratively applying another program retry pulse to the cell and determining whether the cell is programmed, until the cell is programmed within the third program verification margin or a maximum number, N, of retries is made. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. An apparatus having program circuits, coupled to a memory array, supply circuits and a plurality of bit latches for programming a cell on a selected word-line and on bit-lines coupled to a bit latch storing a program value, said apparatus comprising the following circuitry:
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an analog data-line voltage record circuitry for each bit-line decoder and bit-latch; a pulse width control means; a program verification voltage regulating means for each program stage. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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Specification