Semiconductor memory device

• US 6,041,005 A
• Filed: 06/29/1999
• Issued: 03/21/2000
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Yi, Seung Hyun, Kim, Jae Whan
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US09/342,105
• Time in Patent Office: 266 Days
• Field of Search: 365/208, 365/207, 365/226, 365/227, 365/189.01, 365/230.01
• US Class Current: 365/207
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

Abstract

The present invention relates to semiconductor memory device and more particularly, to a technique for stabilizing the potential of the cell plate line by using two kinds of potentials for the cell plate line driver to implement the powerful driving force and rapid operability required in case of designing the RAM using as the memory device the material having large electrostatic capacity, and for preventing the loss of I/O by using CMOS transistors in the decoder circuit which receives the cell plate line voltage by cooperating with the cell plate line driver circuit and feeds back the cell plate line voltage.

Claims

1. A cell plate line driver circuit using a plurality of potentials to stabilize a potential of a cell plate line comprising:

a high voltage application section for applying a high voltage to said cell plate line;

an internal voltage application section for applying an internal voltage to said cell plate line;

a voltage comparison section for comparing a reference cell plate line potential and a potential of an internal voltage and for outputing to said each voltage application section; and

a control section for controlling the operation of said each section.

2. The cell plate line driver circuit of claim 1, wherein said high voltage application section comprises:

a plurality of inverting devices for inverting the signal outputted from said voltage comparison section;

a first switching device for outputting the high voltage to said cell plate line by being turned on/off by the final output signal of said inverting device; and

a second switching device connected to one terminal of said switching device and turned on/off according to the signal outputted from said control section.

3. The cell plate line driver circuit of claim 1, wherein said internal voltage application section comprises:

an operation means for operating a signal outputted from said inverting device in said outputted from said inverting device in said high voltage application section and a signal outputted from said control section;

an inverting device for inverting a signal outputted from said operation means;

a third switching device for outputting an internal voltage to said cell plate line by being turned on/off by the signal outputted from said inverting device.

4. The cell plate line driver circuit of claim 1, wherein said voltage comparison section comprises:

a differential amplifier for receiving and differentially amplifying a reference cell plate line voltage and said internal voltage, applying the high voltage to said cell plate line if said reference cell plate line voltage is lower than said internal voltage and applying said internal voltage to said cell plate line if said reference cell plate line voltage is higher than said internal voltage; and

a plurality of MOS transistors.

5. A decoder circuit in a semiconductor memory for transferring to a cell plate line an output of a cell plate line driver supplying a plurality of voltages comprising:

a selection section for selectively applying to a cell of which a word line is enabled a cell plate line voltage inputted from said cell plate line driver circuit; and

an output section for inputting a reference cell plate line voltage to a voltage comparison section of said cell plate line driver if said cell plate line voltage applied through said selection section is shifted to said reference cell plate line voltage through a cell array; and

wherein switching devices constituting said selection section and output section prevent loss of I/O signal by using CMOS transistors.

6. A semiconductor memory device comprising:

(A) a cell plate line driver circuit using a plurality of potentials to stabilize a potential of a cell plate line comprising;

a high voltage application section for applying a high voltage to said cell plate line;

an internal voltage application section for applying an internal voltage to said cell plate line;

a voltage comparison section for comparing a reference cell plate line potential and a potential of an internal voltage and for outputing to said each voltage application section; and

a control section for controlling the operation of said each section; and

(B) a decoder circuit comprising;

a selection section for selectively applying to a cell of which a word line is enabled a cell plate line voltage inputted from said cell plate line driver circuit; and

an output section for inputting a reference cell plate line voltage to a voltage comparison section of said cell plate line driver if said cell plate line voltage applied through said selection section is shifted to said reference cell plate line voltage through a cell array.