Method and apparatus for embedded read only memory in static random access memory
First Claim
1. A method for programming at last two SRAM cells located in a SRAM array comprising a plurality of memory cells to function as a ROM cell and permanently store a logic state, each of said plurality of memory cells having a ground connection and a pair of bit lines associated with it, said method comprising the steps of:
- connecting said pair of bit lines associated with a first of said plurality of memory cells together;
connecting said pair of bit lines associated with a second of said plurality of memory cells together;
maintaining said ground connection or opening said ground connection of said first of said plurality of memory cells, wherein a signal at said connection of said pair of bit lines associated with said first of said plurality of memory cells will be produced, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection;
maintaining said ground connection or opening said ground connection of said second of said plurality of memory cells, wherein a signal at said connection of said pair of bit lines associated with said second of said plurality of memory cells will be produced, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection;
reading said produced signals at said connection of said pair of bit lines associated with said first of said memory cells and said connection of said pair of bit lines associated with said second of said memory cells; and
outputting a signal based on said read produced signals associated with said stored logic state.
1 Assignment
0 Petitions
Accused Products
Abstract
The present invention is embodied in a method and apparatus which provides a ROM embedded in a SRAM array utilizing the existing support circuitry of the SRAM array. By disabling or not disabling SRAM cells by removing or not removing the ground or power connections to each cell in different combinations, a pair of SRAM cells can be used to permanently store a specified logic state, i.e. function as a ROM cell. Additionally, a single SRAM cell and a reference signal can also be programmed to function as a ROM cell.
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Citations
65 Claims
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1. A method for programming at last two SRAM cells located in a SRAM array comprising a plurality of memory cells to function as a ROM cell and permanently store a logic state, each of said plurality of memory cells having a ground connection and a pair of bit lines associated with it, said method comprising the steps of:
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connecting said pair of bit lines associated with a first of said plurality of memory cells together; connecting said pair of bit lines associated with a second of said plurality of memory cells together; maintaining said ground connection or opening said ground connection of said first of said plurality of memory cells, wherein a signal at said connection of said pair of bit lines associated with said first of said plurality of memory cells will be produced, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection; maintaining said ground connection or opening said ground connection of said second of said plurality of memory cells, wherein a signal at said connection of said pair of bit lines associated with said second of said plurality of memory cells will be produced, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection; reading said produced signals at said connection of said pair of bit lines associated with said first of said memory cells and said connection of said pair of bit lines associated with said second of said memory cells; and outputting a signal based on said read produced signals associated with said stored logic state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for programming a single SRAM cell located in a SRAM array comprising a plurality of memory cells to function as a ROM cell and permanently store a logic state, said single SRAM cell having a ground connection and a pair of bit lines associated with it, said method further comprising the steps of:
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connecting said pair of bit lines together; maintaining said ground connection or opening said ground connection, wherein a signal at said connection of said pair of bit lines will be produced, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection; comparing said signal at said connection of said bit lines with a reference signal; and outputting a signal representing said stored logic state associated with said maintained or opened ground connection. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method for programming a plurality of SRAM cells located in a SRAM array comprising a plurality of memory cells to function as a ROM cell and permanently store a logic state, each of said plurality of memory cells having a first and a second ground connection, said first ground connection being shared with a first adjacent memory cell, said second ground connection being shared with a second adjacent memory cell, each of said memory cells having a pair of bit lines associated with it, said method comprising the steps of:
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maintaining said first ground connection or opening said first ground connection of one of said plurality of memory cells, wherein a signal at a first bit line of said pair of bit lines associated with said one of said memory cells will be produced, said maintaining of said first ground connection causing a different signal at said first bit line of said pair of bit lines than said opening of said first ground connection; maintaining said second ground connection or opening said second ground connection of said one of said plurality of memory cells, wherein a signal at a second bit line of said pair of bit lines associated with said one of said memory cells will be produced, said maintaining of said second ground connection causing a different signal at said second bit line of said pair of bit lines associated with said one of said memory cells than said opening of said second ground connection; reading said produced signals on said first bit line and said second bit line of said pair of bit lines associated with said one of said memory cells; and outputting a signal representing said stored logic state associated with said maintained or opened first and second ground connection. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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24. A semiconductor memory device comprising:
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a plurality of SRAM cells, each of said SRAM cells located in a memory array comprising a plurality of memory cells, each of said plurality of SRAM cells having a ground connection and a pair of bit lines associated with it, said pair of bit lines of a first cell of said plurality of SRAM cells being connected together, said pair of bit lines of a second cell of said plurality of SRAM cells being connected together; a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said first cell, said second input of said one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said second cell, whereby opening or maintaining said ground connection of said first cell and said second cell produces a signal on said connected bit lines to be read by said sense amplifier, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained ground connections of said first cell and said second cell; whereby said first cell and said second cell are programmed to function as a ROM cell and permanently store a logic signal. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31)
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32. A semiconductor memory comprising:
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a plurality of SRAM cells, each of said SRAM cells located in a memory array comprising a plurality of memory cells, each of said plurality of SRAM cells having a ground connection and a pair of bit lines associated with it, said pair of bit lines of a first cell of said plurality of SRAM cells being connected together; a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said first cell, said second input of said one of said plurality of sense amplifiers being connected to a reference signal, whereby opening or maintaining said ground connection of said first cell produces a signal on said connected bit lines to be read by said sense amplifier, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained ground connection of said first cell; whereby said first cell is programmed to function as a ROM cell and permanently store a logic signal. - View Dependent Claims (33, 34, 35, 36, 37, 38)
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39. A semiconductor memory device comprising:
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a plurality of SRAM cells, each of said SRAM cells located in a memory array comprising plurality of memory cells, each of said plurality of memory cells having a first and a second ground connection, said first ground connection being shared with a first adjacent memory cell, said second ground connection being shared with a second adjacent memory cell, each of said memory cells having a pair of bit lines associated with it; a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to a first of said pair of bit lines of a first SRAM cell, said second input of said one of said plurality of sense amplifiers being connected to a second of said pair of bit lines of said first SRAM cell, whereby opening or maintaining said first and said second ground connection of said first cell produces a signal on said first and said second bit lines to be read by said sense amplifier, said maintaining of a ground connection causing a different signal at said bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained first and second ground connections of said first cell; whereby said first cell is programmed to function as a ROM cell and permanently store a logic signal. - View Dependent Claims (40, 41, 42, 43, 44, 45)
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46. A processor system comprising:
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a central processing unit; and a memory device comprising a plurality of SRAM cells, said SRAM cells being located in a memory array comprising a plurality of memory cells, wherein one or more of said SRAM cells is programmed to function as a ROM cell and permanently store a logic state, each of said SRAM cells having a ground connection and a pair of bit lines associated with it, said pair of bit lines of a first cell of said plurality of SRAM cells being connected together, said pair of bit lines of a second cell of said plurality of SRAM cells being connected together; and a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said first cell, said second input of said one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said second cell, whereby opening or maintaining said ground connection of said first cell and said second cell produces a signal on said connected bit lines to be read by said sense amplifier, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained ground connections of said first cell and said second cell; whereby said first cell and said second cell are programmed to function as a ROM cell and permanently store a logic signal. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53)
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54. A processor system comprising:
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a central processing unit; a memory device comprising a plurality of SRAM cells, said SRAM cells being located in a memory array comprising a plurality of memory cells, wherein one or more of said SRAM cells is programmed to function as a ROM cell and permanently store a logic state, each of said SRAM cells having a ground connection and a pair of bit lines associated with it, said pair of bit lines of a first cell of said plurality of SRAM cells being connected together; and a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said first cell, said second input of said one of said plurality of sense amplifiers being connected to a reference signal, whereby opening or maintaining said ground connection of said first cell produces a signal on said connected bit lines to be read by said sense amplifier, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained ground connection of said first cell; whereby said first cell is programmed to function as a ROM cell and permanently store a logic signal. - View Dependent Claims (55, 56, 57, 58, 59)
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60. A processor system comprising:
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a central processing unit; a memory device comprising a plurality of SRAM cells, said SRAM cells being located in a memory array comprising a plurality of memory cells, wherein one or more of said SRAM cells is programmed to function as a ROM cell and permanently store a logic state, wherein each of said plurality of memory cells has a first and a second ground connection, said first ground connection being shared with a first adjacent memory cell, said second ground connection being shared with a second adjacent memory cell, each of said memory cells having a pair of bit lines associated with it; and a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to a first of said pair of bit lines of a first SRAM cell, said second input of said one of said plurality of sense amplifiers being connected to a second of said pair of bit lines of said first SRAM cell, whereby opening or maintaining said first and said second ground connection of said first cell produces a signal on said first and said second bit lines to be read by said sense amplifier, said maintaining of a ground connection causing a different signal at said bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained first and second ground connections of said first cell; whereby said first cell is programmed to function as a ROM cell and permanently store a logic signal. - View Dependent Claims (61, 62, 63, 64, 65)
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Specification