Method and apparatus for embedded read only memory in static random access memory

• US 6,041,008 A
• Filed: 05/13/1998
• Issued: 03/21/2000
• Est. Priority Date: 05/13/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Kenneth W.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/076,730
• Time in Patent Office: 678 Days
• Field of Search: 365/225.7, 365/154, 365/94, 365/96, 365/103
• US Class Current: 365/225.7
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

The present invention is embodied in a method and apparatus which provides a ROM embedded in a SRAM array utilizing the existing support circuitry of the SRAM array. By disabling or not disabling SRAM cells by removing or not removing the ground or power connections to each cell in different combinations, a pair of SRAM cells can be used to permanently store a specified logic state, i.e. function as a ROM cell. Additionally, a single SRAM cell and a reference signal can also be programmed to function as a ROM cell.

Claims

1. A method for programming at last two SRAM cells located in a SRAM array comprising a plurality of memory cells to function as a ROM cell and permanently store a logic state, each of said plurality of memory cells having a ground connection and a pair of bit lines associated with it, said method comprising the steps of:

connecting said pair of bit lines associated with a first of said plurality of memory cells together;

connecting said pair of bit lines associated with a second of said plurality of memory cells together;

maintaining said ground connection or opening said ground connection of said first of said plurality of memory cells, wherein a signal at said connection of said pair of bit lines associated with said first of said plurality of memory cells will be produced, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection;

maintaining said ground connection or opening said ground connection of said second of said plurality of memory cells, wherein a signal at said connection of said pair of bit lines associated with said second of said plurality of memory cells will be produced, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection;

reading said produced signals at said connection of said pair of bit lines associated with said first of said memory cells and said connection of said pair of bit lines associated with said second of said memory cells; and

outputting a signal based on said read produced signals associated with said stored logic state.

2. The method according to claim 1 further comprising:

using a sense amplifier to read said produced signal.

3. The method according to claim 1, wherein said ground connection of said first of said plurality of memory cells is maintained and said ground connection of said second of said plurality of memory cells is opened.

4. The method according to claim 1 wherein said ground connection of said first of said plurality of memory cells is opened and said ground connection of said second of said plurality of memory cells is maintained.

5. The method according to claim 1 further comprising:

breaking a fuse connection to open said ground connection of said first or second of said memory cells.

6. The method according to claim 1, wherein said ground connection of each of said plurality of memory cells is formed from a conductive link, said method further comprising:

severing said conductive link and opening said ground connection of said first or second of said memory cells.

7. The method according to claim 1 further comprising:

opening said ground connection of said first or second of said memory cells during a fabrication process of said memory array.

8. The method according to claim 1, wherein said pair of bit lines associated with said first of said plurality of memory cells are connected together through a first transistor, and said pair of bit lines associated with said second of said plurality of memory cells are connected together through a second transistor.

9. The method according to claim 8, wherein said first and second transistors are enabled by a ROM Enable signal.

10. A method for programming a single SRAM cell located in a SRAM array comprising a plurality of memory cells to function as a ROM cell and permanently store a logic state, said single SRAM cell having a ground connection and a pair of bit lines associated with it, said method further comprising the steps of:

connecting said pair of bit lines together;

maintaining said ground connection or opening said ground connection, wherein a signal at said connection of said pair of bit lines will be produced, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection;

comparing said signal at said connection of said bit lines with a reference signal; and

outputting a signal representing said stored logic state associated with said maintained or opened ground connection.

11. The method according to claim 10 further comprising:

using a sense amplifier to compare said signal at said connection of said bit lines and said reference signal.

12. The method according to claim 10 further comprising:

breaking a fuse connection to open said ground connection.

13. The method according to claim 10, wherein said ground connection is formed through a conductive link, said method further comprising:

severing said conductive link and opening said ground connection.

14. The method according to claim 10 further comprising:

opening said ground connection during a fabrication process of said memory array.

15. The method according to claim 10, wherein said pair of bit lines are connected together through a transistor.

16. The method according to claim 15, wherein said transistor is enabled by a ROM Enable signal.

17. A method for programming a plurality of SRAM cells located in a SRAM array comprising a plurality of memory cells to function as a ROM cell and permanently store a logic state, each of said plurality of memory cells having a first and a second ground connection, said first ground connection being shared with a first adjacent memory cell, said second ground connection being shared with a second adjacent memory cell, each of said memory cells having a pair of bit lines associated with it, said method comprising the steps of:

maintaining said first ground connection or opening said first ground connection of one of said plurality of memory cells, wherein a signal at a first bit line of said pair of bit lines associated with said one of said memory cells will be produced, said maintaining of said first ground connection causing a different signal at said first bit line of said pair of bit lines than said opening of said first ground connection;

maintaining said second ground connection or opening said second ground connection of said one of said plurality of memory cells, wherein a signal at a second bit line of said pair of bit lines associated with said one of said memory cells will be produced, said maintaining of said second ground connection causing a different signal at said second bit line of said pair of bit lines associated with said one of said memory cells than said opening of said second ground connection;

reading said produced signals on said first bit line and said second bit line of said pair of bit lines associated with said one of said memory cells; and

outputting a signal representing said stored logic state associated with said maintained or opened first and second ground connection.

18. The method according to claim 17 further comprising:

using a sense amplifier to read said produced signals.

19. The method according to claim 17, wherein said first ground connection of said one of said memory cells is maintained and said second ground connection of said one of said memory cells is opened.

20. The method according to claim 17 wherein said first ground connection of said one of said memory cells is opened and said second ground connection of said one of said memory cells is maintained.

21. The method according to claim 17 further comprising:

breaking a fuse connection to open said first or said second ground connection of said one of said memory cells.

22. The method according to claim 17, wherein said first and said second ground connection of each of said plurality of memory cells is formed from a conductive link, said method further comprising:

severing said conductive link and opening said first or said second ground connection of said one of said memory cells.

23. The method according to claim 17 further comprising:

opening said first or said second ground connection of said one of said memory cells during a fabrication process of said memory array.

24. A semiconductor memory device comprising:

a plurality of SRAM cells, each of said SRAM cells located in a memory array comprising a plurality of memory cells, each of said plurality of SRAM cells having a ground connection and a pair of bit lines associated with it, said pair of bit lines of a first cell of said plurality of SRAM cells being connected together, said pair of bit lines of a second cell of said plurality of SRAM cells being connected together;

a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said first cell, said second input of said one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said second cell,

whereby opening or maintaining said ground connection of said first cell and said second cell produces a signal on said connected bit lines to be read by said sense amplifier, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained ground connections of said first cell and said second cell;

whereby said first cell and said second cell are programmed to function as a ROM cell and permanently store a logic signal.

25. The semiconductor memory device according to claim 24, wherein said ground connection of said first cell of said plurality of SRAM cells is maintained and said ground connection of said second cell of said plurality of SRAM cells is opened.

26. The semiconductor memory device according to claim 24 wherein said ground connection of said first cell of said plurality of SRAM cells is opened and said ground connection of said second cell of said plurality of SRAM cells is maintained.

27. The semiconductor memory device according to claim 24 further comprising:

a fuse in said ground connection of said first cell or said second cell of said plurality of SRAM cells, whereby opening said fuse opens said ground connection.

28. The semiconductor memory device according to claim 24, wherein said ground connection of each of said plurality of SRAM cells is formed from a conductive link, and said ground connection is opened by using a laser to sever said conductive link.

29. The semiconductor memory device according to claim 24 wherein opening said ground connection of said first cell or said second cell of said SRAM cells is done during a fabrication process of said plurality of SRAM cells.

30. The semiconductor memory device according to claim 24 further comprising:

a first transistor, wherein said pair of bit lines associated with said first cell of said plurality of SRAM cells are connected together through said first transistor; and

a second transistor, wherein said pair of bit lines associated with said second cell of said plurality of SRAM cells are connected together through said second transistor.

31. The semiconductor memory device according to claim 30, wherein said first and second transistors are enabled by a ROM Enable signal.

32. A semiconductor memory comprising:

a plurality of SRAM cells, each of said SRAM cells located in a memory array comprising a plurality of memory cells, each of said plurality of SRAM cells having a ground connection and a pair of bit lines associated with it, said pair of bit lines of a first cell of said plurality of SRAM cells being connected together;

a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said first cell, said second input of said one of said plurality of sense amplifiers being connected to a reference signal,

whereby opening or maintaining said ground connection of said first cell produces a signal on said connected bit lines to be read by said sense amplifier, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained ground connection of said first cell;

whereby said first cell is programmed to function as a ROM cell and permanently store a logic signal.

33. The semiconductor memory device according to claim 32 further comprising:

a fuse in said ground connection of said first cell of said plurality of SRAM cells, whereby opening said fuse opens said ground connection.

34. The semiconductor memory device according to claim 32, wherein said ground connection of each of said plurality of SRAM cells is formed from a conductive link, and said ground connection of said first cell is opened by using a laser to sever said conductive link.

35. The semiconductor memory device according to claim 32, wherein said conductive link is a polysilicon link.

36. The semiconductor memory device according to claim 32 wherein opening said ground connection of said first cell of said SRAM cells is done during a fabrication process of said plurality of SRAM cells.

37. The semiconductor memory device according to claim 32 further comprising:

a first transistor, wherein said pair of bit lines associated with said first cell of said plurality of SRAM cells are connected together through said first transistor.

38. The semiconductor memory device according to claim 37, wherein said first transistor is enabled by a ROM Enable signal.

39. A semiconductor memory device comprising:

a plurality of SRAM cells, each of said SRAM cells located in a memory array comprising plurality of memory cells, each of said plurality of memory cells having a first and a second ground connection, said first ground connection being shared with a first adjacent memory cell, said second ground connection being shared with a second adjacent memory cell, each of said memory cells having a pair of bit lines associated with it;

a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to a first of said pair of bit lines of a first SRAM cell, said second input of said one of said plurality of sense amplifiers being connected to a second of said pair of bit lines of said first SRAM cell,

whereby opening or maintaining said first and said second ground connection of said first cell produces a signal on said first and said second bit lines to be read by said sense amplifier, said maintaining of a ground connection causing a different signal at said bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained first and second ground connections of said first cell;

whereby said first cell is programmed to function as a ROM cell and permanently store a logic signal.

40. The semiconductor memory device according to claim 39, wherein said first ground connection of said first cell is maintained and said second ground connection of said first cell is opened.

41. The semiconductor memory device according to claim 39 wherein said first ground connection of said first cell is opened and said second ground connection of said first cell is maintained.

42. The semiconductor memory device according to claim 39 further comprising:

a fuse in said first and said second ground connection of said first cell, whereby opening said fuse opens said ground connection.

43. The semiconductor memory device according to claim 39, wherein said first and said second ground connection of each of said plurality of SRAM cells is formed from a conductive link, and said first or said second ground connections are opened by severing said conductive link.

44. The semiconductor memory device according to claim 43, wherein said conductive link is a polysilicon link.

45. The semiconductor memory device according to claim 39 wherein opening said first or said second ground connection of said first cell is done during a fabrication process of said plurality of SRAM cells.

46. A processor system comprising:

a central processing unit; and

a memory device comprising a plurality of SRAM cells, said SRAM cells being located in a memory array comprising a plurality of memory cells, wherein one or more of said SRAM cells is programmed to function as a ROM cell and permanently store a logic state, each of said SRAM cells having a ground connection and a pair of bit lines associated with it, said pair of bit lines of a first cell of said plurality of SRAM cells being connected together, said pair of bit lines of a second cell of said plurality of SRAM cells being connected together; and

a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said first cell, said second input of said one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said second cell,

whereby opening or maintaining said ground connection of said first cell and said second cell produces a signal on said connected bit lines to be read by said sense amplifier, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained ground connections of said first cell and said second cell;

whereby said first cell and said second cell are programmed to function as a ROM cell and permanently store a logic signal.

47. The processor system according to claim 46, wherein said ground connection of said first cell of said plurality of SRAM cells is maintained and said ground connection of said second cell of said plurality of SRAM cells is opened.

48. The processor system according to claim 46 wherein said ground connection of said first cell of said plurality of SRAM cells is opened and said ground connection of said second cell of said plurality of SRAM cells is maintained.

49. The processor system according to claim 46, wherein said memory device further comprises:

a fuse in said ground connection of said first cell or said second cell of said plurality of SRAM cells, whereby opening said fuse opens said ground connection.

50. The processor system according to claim 46, wherein said ground connection of each of said plurality of SRAM cells is formed from a conductive link, and said ground connection is opened by severing said conductive link.

51. The processor system according to claim 46 wherein opening said ground connection of said first cell or second cell of said SRAM cells is done during a fabrication process of said plurality of SRAM cells.

52. The processor system according to claim 46, wherein said memory device further comprises:

a first transistor, wherein said pair of bit lines associated with said first cell of said plurality of SRAM cells are connected together through said first transistor; and

a second transistor, wherein said pair of bit lines associated with said second cell of said plurality of SRAM cells are connected together through said second transistor.

53. The processor system according to claim 52, wherein said first and second transistors are enabled by a ROM Enable signal.

54. A processor system comprising:

a central processing unit;

a memory device comprising a plurality of SRAM cells, said SRAM cells being located in a memory array comprising a plurality of memory cells, wherein one or more of said SRAM cells is programmed to function as a ROM cell and permanently store a logic state, each of said SRAM cells having a ground connection and a pair of bit lines associated with it, said pair of bit lines of a first cell of said plurality of SRAM cells being connected together; and

a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to said connected pair of bit lines of said first cell, said second input of said one of said plurality of sense amplifiers being connected to a reference signal,

whereby opening or maintaining said ground connection of said first cell produces a signal on said connected bit lines to be read by said sense amplifier, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained ground connection of said first cell;

whereby said first cell is programmed to function as a ROM cell and permanently store a logic signal.

55. The processor system according to claim 54, wherein said memory device further comprises:

a fuse in said ground connection of said first cell of said plurality of SRAM cells, whereby opening said fuse opens said ground connection.

56. The processor system according to claim 54, wherein said ground connection of each of said plurality of SRAM cells is formed from a conductive link, and said ground connection of said first cell is opened by severing said conductive link.

57. The processor system according to claim 54 wherein opening said ground connection of said first cell of said SRAM cells is done during a fabrication process of said plurality of SRAM cells.

58. The processor system according to claim 54, wherein said memory device further comprises:

a first transistor, wherein said pair of bit lines associated with said first cell of said plurality of SRAM cells are connected together through said first transistor.

59. The processor system according to claim 58, wherein said first transistor is enabled by a ROM Enable signal.

60. A processor system comprising:

a central processing unit;

a memory device comprising a plurality of SRAM cells, said SRAM cells being located in a memory array comprising a plurality of memory cells, wherein one or more of said SRAM cells is programmed to function as a ROM cell and permanently store a logic state, wherein each of said plurality of memory cells has a first and a second ground connection, said first ground connection being shared with a first adjacent memory cell, said second ground connection being shared with a second adjacent memory cell, each of said memory cells having a pair of bit lines associated with it; and

a plurality of sense amplifiers, each having a first and second input and an output, said first input of one of said plurality of sense amplifiers being connected to a first of said pair of bit lines of a first SRAM cell, said second input of said one of said plurality of sense amplifiers being connected to a second of said pair of bit lines of said first SRAM cell,

whereby opening or maintaining said first and said second ground connection of said first cell produces a signal on said first and said second bit lines to be read by said sense amplifier, said maintaining of a ground connection causing a different signal at said bit lines than said opening of said ground connection, and said sense amplifier outputs a signal representative of a stored logic state associated with said opened or maintained first and second ground connections of said first cell;

whereby said first cell is programmed to function as a ROM cell and permanently store a logic signal.

61. The processor system according to claim 60, wherein said first ground connection of said first cell is maintained and said second ground connection of said first cell is opened.

62. The processor system according to claim 60 wherein said first ground connection of said first cell is opened and said second ground connection of said first cell is maintained.

63. The processor system according to claim 60, wherein said memory device further comprises:

a fuse in said first and said second ground connection of said first cell, whereby opening said fuse opens said respective ground connection.

64. The processor system according to claim 60, wherein said first and said second ground connection of each of said plurality of SRAM cells is formed from a conductive link, and said first or said second ground connections are opened by severing said conductive link.

65. The processor system according to claim 60 wherein opening said first or said second ground connection of said first cell is done during a fabrication process of said plurality of SRAM cells.