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Multi-clock matched filter for receiving signals with multipath

  • US 6,041,073 A
  • Filed: 09/18/1998
  • Issued: 03/21/2000
  • Est. Priority Date: 09/18/1998
  • Status: Expired due to Term
First Claim
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1. An improvement, to a spread-spectrum receiver, for receiving, in a multipath environment, a spread-spectrum signal having data spread by a chip-sequence signal, with each chip of the chip-sequence signal having a chip duration, with the spread-spectrum signal arriving from a plurality of paths from the multipath environment, comprising:

  • a clock-signal generator for generating a clock signal, with the clock signal, during a chip duration, having a plurality of phases, with a number of phases of the plurality of phases at least equal to a number of paths of the plurality of paths;

    an analog-to-digital converter for sampling the spread-spectrum signal to generate, during the chip duration, a plurality of chip samples, with a number of chip samples in the plurality of chip samples at least equal to the number of phases in the plurality of phases, said analog-to-digital converter, responsive to each chip sample of the plurality of chip samples, for converting each chip sample to a digital-chip sample, thereby generating a plurality of digital-chip samples;

    a plurality of signal registers, coupled to said analog-to-digital converter, for storing the plurality of digital-chip samples;

    a plurality of gates, coupled between said plurality of signal registers, respectively, and said analog-to-digital converter, each of said plurality of gates responsive to a set of phase signals, respectively, from a multiplicity of sets of phase signals, for passing a respective number of the plurality of digital-chip samples into a respective signal register of the plurality of signal registers;

    a signal-register multiplexer, coupled to each of the plurality of signal registers, said signal-register multiplexer responsive to a register-select signal, for selecting a respective signal register from the plurality of signal registers;

    a matched filter, coupled to said signal-register multiplexer, and having an impulse response matched to the spread-spectrum signal, for detecting an early portion, a punctual portion and a late portion of each chip embedded in the spread-spectrum signal for each path of the plurality of paths, respectively;

    a RAKE-timing generator for generating a plurality of path-select signals corresponding to the plurality of paths from the multipath environment;

    a plurality of delay-locked-loop (DLL) path-tracking circuits, with each DLL path-tracking circuit responsive to a respective path-select signal of the plurality of path-select signals, for gating the early portion and the late portion, corresponding to a respective path, of a detected spread-spectrum signal, into the respective DLL path-tracking circuit, and for generating a DLL signal of a plurality of DLL signals; and

    a plurality of DLL multiplexers coupled to said clock-signal generator, to said plurality of DLL path-tracking circuits, and to said plurality of gates, respectively, each DLL multiplexer of said plurality of DLL multiplexers, responsive to a respective DLL signal from a respective DLL path-tracking circuit, for passing a respective set of phases of the plurality of phases from said clock-signal generator to a respective gate of said plurality of gates, with said plurality of DLL multiplexers thereby generating a multiplicity of sets of phase signals, respectively.

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