Multi-clock matched filter for receiving signals with multipath

• US 6,041,073 A
• Filed: 09/18/1998
• Issued: 03/21/2000
• Est. Priority Date: 09/18/1998
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Golden Bridge Technology Incorporated
• Inventors: Kanterakis, Emmanuel, Tran, Jimmy Cuong, Davidovici, Sorin
• Primary Examiner(s): Vo, Don N.
• Application Number:
  US09/157,300
• Time in Patent Office: 550 Days
• Field of Search: 375/200, 375/206, 375/208, 375/343, 375/347, 370/320, 370/335, 370/342, 370/441
• US Class Current: 375/148
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers

Abstract

A multi-clock matched filter for receiving signals with multipath. The signals may be modulated with a spread-spectrum spreading sequence, or other analog or digital signal. A number of signal registers store digital samples of the received signal. The gating of digital samples into each of the signal registers is controlled by a separate clock timing. The timing sequence may be derived from a common clock. A multiplexer sequentially selects each of the signal registers, and passes the respective content of each signal register to a matched filter. A number of delay-locked-loop circuits track each of the multipath signals, and generate the timing sequence for gating signal registers.

Claims

1. An improvement, to a spread-spectrum receiver, for receiving, in a multipath environment, a spread-spectrum signal having data spread by a chip-sequence signal, with each chip of the chip-sequence signal having a chip duration, with the spread-spectrum signal arriving from a plurality of paths from the multipath environment, comprising:

a clock-signal generator for generating a clock signal, with the clock signal, during a chip duration, having a plurality of phases, with a number of phases of the plurality of phases at least equal to a number of paths of the plurality of paths;

an analog-to-digital converter for sampling the spread-spectrum signal to generate, during the chip duration, a plurality of chip samples, with a number of chip samples in the plurality of chip samples at least equal to the number of phases in the plurality of phases, said analog-to-digital converter, responsive to each chip sample of the plurality of chip samples, for converting each chip sample to a digital-chip sample, thereby generating a plurality of digital-chip samples;

a plurality of signal registers, coupled to said analog-to-digital converter, for storing the plurality of digital-chip samples;

a plurality of gates, coupled between said plurality of signal registers, respectively, and said analog-to-digital converter, each of said plurality of gates responsive to a set of phase signals, respectively, from a multiplicity of sets of phase signals, for passing a respective number of the plurality of digital-chip samples into a respective signal register of the plurality of signal registers;

a signal-register multiplexer, coupled to each of the plurality of signal registers, said signal-register multiplexer responsive to a register-select signal, for selecting a respective signal register from the plurality of signal registers;

a matched filter, coupled to said signal-register multiplexer, and having an impulse response matched to the spread-spectrum signal, for detecting an early portion, a punctual portion and a late portion of each chip embedded in the spread-spectrum signal for each path of the plurality of paths, respectively;

a RAKE-timing generator for generating a plurality of path-select signals corresponding to the plurality of paths from the multipath environment;

a plurality of delay-locked-loop (DLL) path-tracking circuits, with each DLL path-tracking circuit responsive to a respective path-select signal of the plurality of path-select signals, for gating the early portion and the late portion, corresponding to a respective path, of a detected spread-spectrum signal, into the respective DLL path-tracking circuit, and for generating a DLL signal of a plurality of DLL signals; and

a plurality of DLL multiplexers coupled to said clock-signal generator, to said plurality of DLL path-tracking circuits, and to said plurality of gates, respectively, each DLL multiplexer of said plurality of DLL multiplexers, responsive to a respective DLL signal from a respective DLL path-tracking circuit, for passing a respective set of phases of the plurality of phases from said clock-signal generator to a respective gate of said plurality of gates, with said plurality of DLL multiplexers thereby generating a multiplicity of sets of phase signals, respectively.

2. The improvement as set forth in claim 1, with each DLL path-tracking circuit including:

an early register for storing the early portion;

an early absolute-value circuit, coupled to said early register, for generating an early-absolute value from the early portion;

a late register for storing the late portion;

a late absolute-value circuit, coupled to said late register, for generating a late-absolute value from the late portion;

a subtraction circuit, coupled to said early absolute-value circuit and to said late absolute-value circuit, for generating a difference signal from the early-absolute value and the late-absolute value; and

a counter, coupled to said subtraction circuit, for generating, responsive to the difference signal, the respective DLL signal.

3. The improvement as set forth in claim 1 or 2, with the matched filter including:

a reference register for storing a replica of the chip-sequence signal of the spread-spectrum signal;

a filter multiplexer, coupled to said signal-register multiplexer and to said reference register, for multiplying the replica of the chip-sequence signal by an output selected by said signal-register multiplexer, thereby generating a plurality of multiplier-output signals; and

an adder tree, coupled to said filter multiplexer, for combining the plurality of multiplier-output signals from said filter multiplexer, thereby generating the early portion, the punctual portion and the late portion of the spread-spectrum signal for each path of the plurality of paths, respectively.

4. The improvement as set forth in claim 1 or 2, further including:

a plurality of Costas loops, coupled to said matched filter and to said RAKE-timing generator, for generating a plurality of detection signals, each Costas loop of the plurality of Costas loops responsive to a respective path-select signal from said RAKE-timing generator, and to the punctual portion of the spread-spectrum signal of each path of the plurality of paths, for generating a detection signal; and

a maximal-ratio combiner coupled to the plurality of Costas loops, for maximal ratio combining the plurality of detection signals.

5. An improvement, to a spread-spectrum receiver, for receiving, in a multipath environment, a spread-spectrum signal having data spread by a chip-sequence signal, with each chip of the chip-sequence signal having a chip duration, with the spread-spectrum signal arriving from a plurality of paths from the multipath environment, comprising:

clock-signal means for generating a clock signal, with the clock signal, during a chip duration, having a plurality of phases, with a number of phases of the plurality of phases at least equal to a number of paths of the plurality of paths;

converter means for sampling the spread-spectrum signal to generate, during the chip duration, a plurality of chip samples, with a number of chip samples in the plurality of chip samples at least equal to the number of phases in the plurality of phases, said converter means, responsive to each chip sample of the plurality of chip samples, for converting each chip sample to a digital-chip sample;

register means for storing a plurality of digital-chip samples;

gate means coupled between said register means and said converter means, said gate means responsive to a set of phase signals from a multiplicity of sets of phase signals, for passing a respective number of the plurality of digital-chip samples into a respective signal register of the register means;

signal-multiplexer means coupled to said register means, said signal-multiplexer means responsive to a register-select signal, for selecting a respective signal register from said register means;

matched-filter means, coupled to said signal-multiplexer means and having an impulse response matched to the spread-spectrum signal, for detecting an early portion, a punctual portion and a late portion of each chip embedded in the spread-spectrum signal for each path of the plurality of paths, respectively;

RAKE generator means for generating a plurality of path-select signals corresponding to the plurality of paths from the multipath environment;

delay-locked-loop (DLL) means, responsive to a respective path-select signal from the plurality of path-select signals, for gating the early portion and the late portion, corresponding to a respective path, of a detected spread-spectrum signal, into the DLL means, and for generating a DLL signal of a plurality of DLL signals; and

DLL multiplexer means, coupled to said clock-signal means, to said DLL means, and to said gate means, and responsive to a respective DLL signal from said DLL means, for passing a respective set of phases of the plurality of sets of phases from said clock-signal means to said gate means, with said DLL multiplexer means thereby generating a multiplicity of sets of phase signals, respectively.

6. The improvement as set forth in claim 5, with said DLL means comprising a plurality of DLL multiplexers, each DLL multiplexer including:

an early register for storing the early portion;

an early absolute-value circuit, coupled to said early register, for generating an early-absolute value from the early portion;

a late register for storing the late portion;

a late absolute-value circuit, coupled to said late register, for generating a late-absolute value from the late portion;

a subtraction circuit, coupled to said early absolute-value circuit and to said late absolute-value circuit, for generating a difference signal from the early-absolute value and the late-absolute value; and

a counter, coupled to said subtraction circuit, for generating, responsive to the difference signal, the respective DLL signal.

7. The improvement as set forth in claim 5 or 6, with said matched-filter means including:

a reference register for storing a replica of the chip-sequence signal of the spread-spectrum signal;

a filter multiplexer, coupled to said signal-multiplexer means and to said reference register, for multiplying the replica of the chip-sequence signal by an output selected by said signal-multiplexer means, thereby generating a plurality of multiplier-output signals; and

an adder tree, coupled to said filter multiplexer, for combining the plurality of multiplier output signals from said filter multiplexer, thereby generating the early portion, punctual portion and late portion of the spread-spectrum signal for each path of the plurality of paths, respectively.

8. The improvement as set forth in claim 5 or 6, further including:

a plurality of Costas loops coupled to said matched filter means and to said RAKE generator means, for generating a plurality of detection signals, each Costas loop of the plurality of Costas loops responsive to a respective path-select signal from said RAKE generator means, and to the punctual portion of the spread-spectrum signal of each path of the plurality of paths, for generating a detection signal; and

a maximal-ratio combiner coupled to the plurality of Costas loops, for maximal ratio combining the plurality of detection signals.

9. A method for improving a spread-spectrum receiver for receiving, from a multipath environment, a spread-spectrum signal having data spread by a chip-sequence signal, with each chip of the chip-sequence signal having a chip duration, with the spread-spectrum signal arriving from a plurality of paths from the multipath environment, comprising the steps of:

generating a clock signal, with the clock signal, during a chip duration, having a plurality of phases, with a number of phases of the plurality of phases at least equal to a number of paths of the plurality of paths;

sampling the spread-spectrum signal to generate, during the chip duration, a plurality of chip samples, with a number of chip samples in the plurality of chip samples at least equal to the number of phases in the plurality of phases;

converting, in response to each chip sample of the plurality of chip samples, each chip sample to a digital-chip sample;

storing a plurality of digital-chip samples in a plurality of signal registers;

passing, through a plurality of gates, a respective number of the plurality of digital-chip samples into a respective signal register of the plurality of signal registers;

selecting a respective signal register from the plurality of signal registers;

detecting an early portion, a punctual portion and a late portion of each chip embedded in the spread-spectrum signal for each path of the plurality of paths, respectively;

generating a plurality of path-select signals corresponding to the plurality of paths from the multipath environment;

gating the early portion and the late portion, corresponding to a respective path, of the detected spread-spectrum signal, for generating a DLL signal of a plurality of DLL signals; and

passing, in response to a respective DLL signal, a respective set of phases of the plurality of phases to a respective gate of said plurality of gates.

10. The improvement as set forth in claim 9, with the step of gating the early portion and the late portion including the steps of:

storing the early portion;

generating an early-absolute value from the early portion;

storing the late portion;

generating a late-absolute value from the late portion;

generating a difference signal from the early-absolute value and the late-absolute value; and

generating, in response to the difference signal, the respective DLL signal.

11. The improvement as set forth in claim 9 or 10, with the step of detecting the early portion, the punctual portion and the late portion, including the steps of:

storing a replica of the chip-sequence signal of the spread-spectrum signal;

multiplying the replica of the chip-sequence signal by an output of the step of selecting a respective signal register, thereby generating a plurality of multiplier-output signals; and

combining the plurality of multiplier-output signals, thereby generating the early portion, the punctual portion and the late portion of the spread-spectrum signal for each path of the plurality of paths, respectively.

12. The improvement as set forth in claim 9 or 10, further including the steps of:

generating a plurality of detection signals in response to a respective path-select signal and to the punctual portion of the spread-spectrum signal of each path of the plurality of paths; and

maximal-ratio combining the plurality of detection signals.