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Data sampling and recover in a phase-locked loop (PLL)

  • US 6,041,090 A
  • Filed: 11/14/1997
  • Issued: 03/21/2000
  • Est. Priority Date: 08/09/1995
  • Status: Expired due to Term
First Claim
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1. A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising:

  • a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks said bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks said bits 1, 1+n, 1+2n, . . . , where n is an odd integer.

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