Data sampling and recover in a phase-locked loop (PLL)
First Claim
1. A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising:
- a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks said bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks said bits 1, 1+n, 1+2n, . . . , where n is an odd integer.
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Accused Products
Abstract
A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising: a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks bits 1, 1+n, 1+2n, . . . . Also, a PLL circuit for recovering a clock signal from incoming data, comprising: a clock generator for generating an odd number, n, of phase-shifted adjacent clock signals; a data sampler for sampling the incoming data; a first pair of outputs from the sampler, for use in a phase detector (along with a reference clock of the adjacent clock signals and the incoming data), capable of producing an adjustment output. Another characterization is a method for recovering data in a PLL comprising the steps of: generating n phase-shifted adjacent clock signals for sampling bits incoming to the PLL; wherein a first of the adjacent clock signals clocks bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks bits 1, 1+n, 1+2n, . . . . Similarly, a third of the adjacent clock signals can be used to clock bits 2, 2+n, 2+2n, . . . , as well as a fourth and fifth of the adjacent clock signals.
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Citations
25 Claims
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1. A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising:
a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks said bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks said bits 1, 1+n, 1+2n, . . . , where n is an odd integer. - View Dependent Claims (2)
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3. A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising:
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a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks said bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks said bits 1, 1+n, 1+2n, . . . ; and a first pair of outputs from said sampler having been produced from two of the adjacent clock signals for use in a first phase detector. - View Dependent Claims (4)
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5. A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising:
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a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks said bits 0, 0+n;
0+2n, . . . , and a second of the adjacent clock signals clocks said bits 1, 1+n, 1+2n, . . . , wherein a pair of the adjacent clock signals, one of which is the reference clock, is used in a first phase detector; andsaid first phase detector further comprises a logic-AND device for operating on a first pair of outputs from said sampler, one of which having been inverted, and a first latch for sampling the reference clock with the incoming data. - View Dependent Claims (6)
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7. A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising:
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a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks said bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks said bits 1, l+n, 1+2n, . . . , wherein a phase adjustment output of the circuit is for a current-type charge pump connected in series with a loop filter and an n-stage voltage-controlled oscillator (VCO) having generated the adjacent clock signals; and a second phase detector in series with a second charge pump, both of which are connected in parallel with a first phase detector and said current-type charge pump, wherein a second pair of outputs from said sampler, at least one of said second pair different from said first pair of outputs, is used in said second phase detector along with a second reference clock signal of the adjacent clock signals and the incoming data.
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8. A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising:
a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks said bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks said bits 1, 1+n, 1+2n, . . . , wherein; a phase adjustment output of the circuit is for a charge pump connected in series with an n=5-stage voltage-controlled oscillator (VCO) having generated the adjacent clock signals; and a third of the adjacent clock signals clocks said bits 2, 2+n, 2+2n, . . . , a fourth of the adjacent clock signals clocks said bits 3, 3+n, 3+2n, . . . , and a fifth of the adjacent clock signals clocks said bits 4, 4+n, 4+2n, . . . . - View Dependent Claims (9)
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10. A phase-locked loop (PLL) circuit for recovering a clock signal from incoming data, comprising:
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a clock generator for generating an odd number, n, of phase-shifted adjacent clock signals; a data sampler for sampling the incoming data; and a first pair of outputs from said sampler for use in a first phase detector along with a reference clock of said adjacent clock signals and the incoming data, said phase detector capable of producing an adjustment output for said clock generator. - View Dependent Claims (11, 12, 13)
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14. A method for recovering data in a phase-locked loop (PLL) comprising the steps of:
generating n phase-shifted adjacent clock signals for sampling bits incoming to the PLL;
wherein a first of said adjacent clock signals clocks said bits 0, 0+n, 0+2n, . . . , and a second of said adjacent clock signals clocks said bits 1, 1+n, 1+2n, wherein n is an odd number.- View Dependent Claims (15, 16, 17)
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18. A method for recovering data in a phase-locked loop (PLL) comprising the steps of:
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generating n phase-shifted adjacent clock signals for sampling bits incoming to the PLL;
wherein a first of said adjacent clock signals clocks said bits 0, 0+n, 0+2n, and a second of said adjacent clock signals clocks said bits 1, 1+n, 1+2n, . . . , wherein n is an odd number, said step of generating comprises using an n-stage voltage-controlled oscillator (VCO) operating at a trimmed frequency close to 1/n times the frequency of said bits;using a third of said adjacent clock signals to clock said bits 2, 2+n, 2+2n, . . . ; using a fourth of said clock signals to clock said bits 3, 3+n, 3+2n, . . . , and using a fifth of said clock signals to clock said bits 4, 4+n, 4+2n, . . . ; detecting whether a reference clock of said adjacent clock signals is aligned with said bits, wherein said step of detecting further comprises the steps of; operating, using a logic-AND device, on a first pair of said sampled outputs, one of which having first been inverted; sampling said reference clock with said bits for input into each of a first and second flip-flop; and sampling an output of each of said first and second flip-flops with said reference clock to produce any requisite phase adjustment output; and outputting the data from the PLL.
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19. A method for recovering data in a phase-locked loop (PLL) comprising the steps of:
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generating n phase-shifted adjacent clock signals for sampling bits incoming to the PLL;
wherein a first of said adjacent clock signals clocks said bits 0, 0+n, 0+2n, . . . , and a second of said adjacent clock signals clocks said bits 1, 1+n, 1+2n, . . . ;detecting whether a reference clock of said adjacent clock signals is aligned with said bits, and in the event of non-alignment, producing a phase adjustment output to adjust phase of the reference clock, wherein said step of detecting further comprises the steps of using a first pair of said sampled outputs, a reference clock of said adjacent clock signals, and said bits to produce said phase adjustment output; and making any requisite phase adjustments to the PLL. - View Dependent Claims (20)
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21. A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising:
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a first pair of clocked outputs from a data sampler for use in a first phase detector along with the reference clock signal; and a second pair of clocked outputs from said sampler, at least one of said second pair different from said first pair, used in a second phase detector along with a second reference clock signal of the adjacent clock signals. - View Dependent Claims (22, 23, 24, 25)
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Specification