Apparatus and method for analyzing passive circuits using reduced-order modeling of large linear subcircuits

• US 6,041,170 A
• Filed: 07/31/1997
• Issued: 03/21/2000
• Est. Priority Date: 07/31/1997
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Feldmann, Peter, Freund, Roland W.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/904,233
• Time in Patent Office: 964 Days
• Field of Search: 395/500.23, 395/500.03, 395/500.34
• US Class Current: 703/2
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method and apparatus for generating and analyzing a reduced-order model of a linear circuit. The method and apparatus generates the symmetric multi-port transfer function of an RLC circuit. The invention employs a novel symmetric block-Lanczos-type procedure, termed SyMPVL for Symmetric Matrix Pade via Lanczos, to reduce original circuit matrices to a pair of banded symmetric matrices. When the circuit comprises only two of the three RLC components, the matrices are also positive definite. These matrices are typically much smaller than the original circuit matrices and determine a reduced-order model of the original multi-port transfer function of the circuit. The reduced transfer function represents a matrix-Pade approximation of the original multi-port matrix transfer function.

Claims

1. An apparatus comprising:

a processing unit having;

a first program for generating a symmetric matrix transfer function relating to a matrix transfer function associated with circuit characteristic data representing a circuit;

a second program for generating a frequency response signal as a function of the matrix transfer function data; and

a processor for executing the programs; and

an output device for displaying said circuit frequency response signal.

2. An apparatus as set forth in claim 1 wherein said symmetric matrix transfer function is guaranteed to be stable and passive when said circuit is an RL, RC or LC circuit.

3. The apparatus of claim 1 wherein the processor, responsive to execution of the first program, calculates characteristic matrix data representing parameters associated with characteristic matrices of the circuit characteristic data, and determines the symmetric matrix Pade approximant from the characteristic matrix data.

4. The apparatus of claim 3 wherein the processor, responsive to execution of the first program, processes the matrix characteristic data to reduce the characteristic matrices and to determine the symmetric matrix Pade approximant therefrom.

5. The apparatus of claim 4 wherein the processor, executing the first program, processes the characteristic matrix data using a symmetric block-Lanczos type procedure.

6. The apparatus of claim 5 wherein the processor, executing the first program, iteratively processes the characteristic data to iteratively reduce the characteristic matrix data using a symmetric block-Lanczos type procedure with look-ahead.

7. The apparatus of claim 1 wherein said processing unit further comprises a second program for generating a frequency response signal using the matrix transfer function data according to a frequency response transfer function, ##EQU20## where T_n is a banded n by n matrix, s is complex frequency, Δ

_n is a diagonal n by n matrix, and ρ

_n is an n by p matrix and are obtained from the circuit characteristic data via a Lanczos type procedure and wherein said processor also executes said second program.

8. An apparatus as set forth in claim 7 wherein said circuit characteristic data is represented by matrices B, C and G and further wherein

9. An apparatus as set forth in claim 7 wherein

10. An apparatus as set forth in claim 7 wherein the frequency response transfer function is

11. An apparatus for generating a frequency response signal indicative of a frequency response of a circuit, the apparatus comprising:

a data source providing circuit characteristic data representing the circuit; and

a processing unit having;

a memory for receiving and storing the circuit characteristic data from the data source;

a set of at least one program including a symmetric Matrix Pade via Lanczos type (SyMPVL) program for generating a symmetric matrix Pade approximant of a transfer function relating to the circuit characteristic data;

a processor for executing the SyMPVL program; and

means for generating the frequency response signal in response to the symmetric matrix Pade approximant.

12. The apparatus of claim 11 wherein the processor, executing the SyMPVL program, calculates characteristic matrix data representing parameters associated with characteristic matrices of the circuit characteristic data, and determines the symmetric matrix Pade approximant from the characteristic matrix data by a block-Lanczos type procedure.

13. The apparatus of claim 12 wherein the processor, executing the SyMPVL program, processes the matrix characteristic data to reduce the characteristic matrices using a plurality of Lanczos vectors and to determine the symmetric matrix Pade approximant therefrom.

14. The apparatus of claim 13 wherein the processor, executing the SyMPVL program, processes the characteristic matrix data using the symmetric block-Lanczos type procedure on the plurality of Lanczos vectors.

15. The apparatus of claim 14 wherein the processor, executing the SyMPVL program, iteratively processes the characteristic matrix data and the plurality of Lanczos vectors to iteratively reduce the characteristic matrix data using a symmetric block-Lanczos type procedure with look-ahead.

16. An apparatus as set forth in claim 15 wherein said circuit characteristic data is represented by matrices B, C and G and further wherein

17. An apparatus as set forth in claim 15 wherein

18. An apparatus as set forth in claim 15 wherein the frequency response transfer function is

19. A circuit analyzer for generating a graphic representation of a predicted performance of a circuit, the circuit analyzer comprising:

an input device for inputting a plurality of circuit parameters representing the circuit;

memory for receiving and storing the circuit parameters;

a processor for executing stored programs and including;

means for generating matrix characteristic data representing a transfer function of the circuit;

means for performing a block-Lanczos type procedure on the matrix characteristic data;

means for calculating a symmetric matrix Pade approximant of the transfer function of the circuit;

means for generating the graphic representation from the symmetric matrix Pade approximant to predict the performance of the circuit; and

a display for displaying the graphic representation.

20. The circuit analyzer of claim 19 wherein the block-Lanczos type procedure performing means performs the block-Lanczos type procedure with look-ahead using the matrix characteristic data.

21. The circuit analyzer of claim 20 wherein the block-Lanczos type procedure performing means iteratively generates a plurality of intermediate parameters from the processed circuit parameters and stores the generated intermediate parameters in the memory.

22. The circuit analyzer of claim 21 wherein the intermediate parameters of an n^th iteration are used by the block-Lanczos type procedure performing means to generate an (n+1)^TH iteration of intermediate parameters.

23. The circuit analyzer of claim 22 wherein the block-Lanczos type procedure performing means generates matrix data representing a banded n by n matrix, T_n, a diagonal n by n matrix, Δ

_n, and an n by p matrix, _n, from the stored intermediate parameters, where n is an integer corresponding to a number of iterations and p is an integer corresponding to a number of electrical connection points of said circuit externally of said circuit.

24. A method for generating a frequency response signal of a circuit, the method comprising the steps of:

providing circuit characteristic data associated with the circuit;

generating characteristic matrix data associated with the circuit characteristic data representing parameters associated with characteristic matrices of the circuit characteristic data;

generating a symmetric matrix transfer function data relating to a matrix transfer function associated with the characteristic matrix data; and

generating the frequency response signal in response to the matrix transfer function data.

25. The method of claim 24 wherein the step of generating the frequency response signal includes the step of determining a frequency response transfer function ##EQU21## where T_n is a banded n by n matrix, s is complex frequency, Δ

_n is a diagonal n by n matrix, ρ

_n is an n by p matrix and are obtained from the circuit characteristic data via a Lanczos type procedure.

26. A method for analyzing a circuit to predict performance of a circuit, comprising the steps of:

receiving from an input device a plurality of circuit parameters representing the circuit;

processing the circuit parameters to generate characteristic matrix data representing parameters associated with characteristic matrices;

performing a block-Lanczos type procedure on the processed parameters to generate a plurality of Lanczos vectors;

calculating a symmetric matrix Pade approximant of a transfer function of the circuit from the plurality of Lanczos vectors;

generating a graphic representation from the symmetric matrix Pade approximant to predict the performance of the circuit; and

displaying the graphic representation on a display.

27. The method of claim 26 wherein the step of performing the block-Lanczos type procedure includes performing look-ahead using matrix characteristic data.

28. An apparatus as set forth in claim 27 wherein the frequency response transfer function is ##EQU22## for RL, RC and LC circuits, where T_n is a banded n by n matrix;

s is complex frequency;

ρ

_n is an n by p matrix; and

I_n is an n by n identity matrix.

29. The method of claim 26 wherein the step of performing the block-Lanczos type procedure includes the steps of:

iteratively generating a plurality of intermediate parameters from the processed parameters; and

storing the generated intermediate parameters in a memory.

30. The method of claim 29 wherein the step of performing the block-Lanczos type procedure includes the step of generating matrix data representing a matrix transfer function from the stored intermediate parameters.

31. An apparatus as set forth in claim 30 wherein ##EQU23## when said circuit is an RL, RC or LC circuit, where

T_n is a banded n by n matrix;

s is complex frequency;

y represents any complex vector,

I_n is an n by n identity matrix, and

_N is a set of complex vectors of length n.

32. An apparatus as set forth in claim 30 wherein said circuit characteristic data is represented by matrices B, C and G and further wherein

33. An apparatus comprising:

a processing unit having;

a memory for storing circuit characteristic data representing a circuit;

a first program for generating a symmetric matrix transfer function relating to a matrix transfer function associated with circuit characteristic data representing a circuit;

a second program for generating a frequency response signal as a function of the matrix transfer function data; and

a processor for executing the programs.

34. An apparatus comprising:

a processing unit having;

a memory for storing circuit characteristic data representing a circuit;

a program for generating a symmetric matrix transfer function relating to a matrix transfer function associated with circuit characteristic data representing a circuit;

a processor for executing the programs; and

means for generating a frequency response signal in response to the matrix transfer function data.