Parallel and serial debug port on a processor

• US 6,041,406 A
• Filed: 12/19/1997
• Issued: 03/21/2000
• Est. Priority Date: 04/08/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Mann, Daniel
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/994,518
• Time in Patent Office: 823 Days
• Field of Search: 714/726, 714/30, 714/47, 714/34, 714/25, 714/40, 714/744, 714/38, 714/736, 714/733, 714/35, 327/277, 327/30, 327/296, 712/35, 712/227, 395/704, 709/102
• US Class Current: 712/227
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 2201/865 Monitoring of software
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches

Abstract

A processor has both a serial debug port and a parallel debug port. The processor includes a processor core. The serial debug port is formed of a plurality of pins configured to send and receive signals to and from external software debug equipment. The parallel debug port is formed of a plurality of pins and configured to send and receive signals from external software debug equipment. A plurality of debug registers are accessible to the serial debug port and the parallel debug port. The debug registers are also coupled to the processor core for receiving and providing debug data and control signals. The processor core performs various software debug operations in response to signals from the external software debug equipment sent over one of the parallel and serial debug ports and communicates the results of the debug operation back over one of the serial and parallel debug ports.

Claims

1. A processor comprising:

a processor core;

a serial debug port formed of a plurality of pins configured to send and receive signals to and from external debug equipment;

a parallel debug port formed of a plurality of pins configured to send and receive signals to and from external debug equipment;

a plurality of debug registers accessible to said serial port and said parallel debug port, and coupled to said processor core for receiving and providing debug data and control signals;

an on-chip trace memory coupled to said processor core and said serial debug port, said trace memory for storing trace information indicative of program execution order in said processor core;

wherein said processor core performs debug operations in response to signals from said external debug equipment sent over one of said parallel and serial debug ports.

2. The processor of claim 1, wherein said serial debug port includes conventional JTAG signals TMS, TCK, TDI and TDO.

3. The processor of claim 1, wherein the contents of said debug registers are coupled to be examined by said debug equipment without halting normal processor operation via said serial debug port.

4. The processor as recited in claim 1 wherein said pins of said parallel debug port includes pins providing a read/write control line, a bus request line and a bus grant line for coupling to said external debug equipment.

5. The processor as recited in claim 1 wherein said pins of said parallel debug port includes pins providing 16 bits of data in parallel.

6. The processor as recited in claim 1 wherein the processor is coupled to said debug equipment via both said serial and parallel debug ports.

7. A method of sending and receiving debug information between a processor-based device and external debug equipment, comprising:

sending debug information serially to and from a serial debug port in the processor-based device;

providing a trace memory in said processor-based device, said trace memory storing information indicative of an order in which instructions are executed by said processor based device;

providing a parallel debug port formed of a plurality of pins configured to send and receive debug signals in parallel;

accessing one of a plurality of debug registers via one of said serial and parallel debug ports, said debug registers being accessible to both said serial debug port and said parallel debug port;

performing a debug operation in said processor-based device in response to signals received at one of said parallel and serial debug ports; and

communicating results of said debug operation from said processor-based device over one of said parallel and serial debug ports.

8. The method as recited in claim 7 wherein said serial debug port provides data over a serial data out line to said external software debug controller and receives data over a serial data in line from said external software debug controller.

9. The method as recited in claim 7 further comprising providing, a read/write control line, a bus request line and a bus grant line on said parallel port for coupling to said external software debug controller.

10. The method as recited in claim 7 wherein said parallel debug port sends and receives at least 16 data bits in parallel.

11. The method as recited in claim 7 further comprising sending a debug command via said serial debug port to enable said parallel debug port.

12. The method as recited in claim 11 further comprising sending debug information to and from said parallel debug port after said parallel debug port has been enabled via said debug command sent via said serial debug port.

13. A method for enabling a debug port in a processor-base device, the processor-based device including a serial debug port and a parallel debug port, the method comprising:

receiving debug information serially into said serial debug port to enable said parallel debug port; and

accessing one of a plurality of debug registers in said processor-based device via said parallel debug port after said parallel debug port has been enabled.

14. A processor comprising:

a processor core;

a serial debug port formed of a plurality of pins configured to send and receive signals to and from external debug equipment;

a parallel debug port formed of a plurality of pins for communicating with external debug equipment, wherein said pins of said parallel debug port include a read/write control line, a bus request line and a bus grant line for coupling to said external debug equipment; and

a plurality of debug registers for receiving and providing debug data and control signals accessible to said serial port and said parallel debug port, and coupled to said processor core.