System for test data storage reduction

• US 6,041,429 A
• Filed: 08/04/1993
• Issued: 03/21/2000
• Est. Priority Date: 06/07/1990
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: International Business Machines Corporation
• Inventors: Koenemann, Bernd Karl Ferdinand
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US08/101,641
• Time in Patent Office: 2,421 Days
• Field of Search: 371/27, 371/21.2, 371/22.3, 714/738, 714/719, 714/720, 714/726, 714/727, 714/735
• US Class Current: 714/738
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer

Abstract

A seed skipping mechanism is provided for use in conjunction with a linear feedback shift register used as a pseudo-random pattern generator for generating sequences of test bit streams for testing integrated circuit devices. The utilization of seed skipping for the pseudo-random pattern number generator in connection with weighting of the patterns from the random pattern generator provides an effective and low cost solution to data storage problems associated with generating effective test patterns for testing integrated circuit chip devices.

Claims

1. A circuit for generating sequences of test pattern bits, especially for application to large integrated circuit chips and systems designed with at least one scan path for testing, said circuit comprising:

pseudo-random pattern generator means including a plurality of register elements and a means for cycling said generator means so as to provide an output bit stream;

weighting means for receiving said output bit stream from said pattern generator and for generating bit sequences having a selectively biased probability distribution of zeroes and ones in the bit sequences from said weighting means;

reseeding means for generating seed values to be loaded into the register elements within said pseudo-random pattern generator means at the beginning of new output bit streams; and

seed skipping means for causing said reseeding means to depart from a pre-established seed sequence by skipping over specified numbers of otherwise generated seed values.

2. The circuit of claim 1 in which said pseudo-random pattern generator comprises a linear feedback shift register.

3. The circuit of claim 1 in which said seed skipping means includes a decrementing counter connected to a memory element containing entries indicative of the number of seed values to skip.

4. A method for testing a digital circuit device, said method comprising the steps of:

simulating test results, for a model of a digital circuit to be tested, using simulated test pattern bit streams generated in accordance with a weighted, pseudo-random process having selectable seed values;

determining from said simulating step which seed values from a sequence of seed values produce test results which are effective for detecting error conditions in said digital circuit;

storing, in a memory element, values which are indicative of which seed values in said sequence are to be skipped as a result of said effectiveness determining step; and

applying a weighted, pseudo-random test pattern bit stream to an actual digital circuit device, said test pattern being generated using a reduced seed sequence based upon said skipping indicators in said memory element.