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System for test data storage reduction

  • US 6,041,429 A
  • Filed: 08/04/1993
  • Issued: 03/21/2000
  • Est. Priority Date: 06/07/1990
  • Status: Expired due to Term
First Claim
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1. A circuit for generating sequences of test pattern bits, especially for application to large integrated circuit chips and systems designed with at least one scan path for testing, said circuit comprising:

  • pseudo-random pattern generator means including a plurality of register elements and a means for cycling said generator means so as to provide an output bit stream;

    weighting means for receiving said output bit stream from said pattern generator and for generating bit sequences having a selectively biased probability distribution of zeroes and ones in the bit sequences from said weighting means;

    reseeding means for generating seed values to be loaded into the register elements within said pseudo-random pattern generator means at the beginning of new output bit streams; and

    seed skipping means for causing said reseeding means to depart from a pre-established seed sequence by skipping over specified numbers of otherwise generated seed values.

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