Method of manufacturing a circuit board having metal bumps and a semiconductor device package comprising the same

• US 6,041,495 A
• Filed: 06/01/1998
• Issued: 03/28/2000
• Est. Priority Date: 06/24/1997
• Status: Expired due to Term

• Current Assignee: Intellectual Discovery Co., Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yong, Hong, In Pyo, Park, Gi Bum, Chung, Myung Kee, Yoon, Jin Hyun
• Primary Examiner(s): Young, Lee
• Assistant Examiner(s): NGUYEN, BINH AN DUC
• Application Number:
  US09/087,929
• Time in Patent Office: 666 Days
• Field of Search: 29/840, 29/841, 29/842, 29/827, 29/829, 29/830, 29/831, 29/832, 257/673, 257/683, 257/689
• US Class Current: 29/841
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/0347 : Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
• CPC Class Codes: H05K 2201/0355 : Metal foils
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump
• CPC Class Codes: H05K 2201/0379 : Stacked conductors
• CPC Class Codes: H05K 2201/0394 : Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
• CPC Class Codes: H05K 2201/09563 : Metal filled via
• CPC Class Codes: H05K 2203/0369 : Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
• CPC Class Codes: H05K 2203/0542 : Continuous temporary metal layer over metal pattern
• CPC Class Codes: H05K 3/064 : Photoresists
• CPC Class Codes: H05K 3/244 : Finish plating of conductors, especially of copper conductors, e.g. for pads or lands selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3457, e.g. by plating H05K3/3473
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/423 : characterised by electroplating method
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

A first method of manufacturing a printed circuit board includes steps of (a) preparing a board which has a chip mounting area and circuit patterns on an upper surface and metal pads to be electrically connected to the circuit patterns on a lower surface, (b) attaching a metal plate to the lower surface of the board, (c) forming metal patterns on the metal pads by etching the metal plate, and (d) forming metal bumps by plating the metal patterns. A second method of manufacturing a circuit board, in this case a flexible circuit board, includes the steps of (a) preparing a board having Cu patterns, plated with a Au layer, attached to a lower surface of a polyimide tape, (b) forming a plurality of via holes in the polyimide tape, which expose the Cu patterns to the upper surface of the polyimide tape, (c) coating the upper surface of the polyimide tape with a photoresist, and exposing and developing the photoresist to form openings therein which expose the via holes, (d) plating walls, defining the openings and the via holes, with Cu, (e) removing remaining portions of the photoresist to produce Cu bumps, and (f) plating the bumps to protect the Cu. The printed circuit boards of the present invention have advantages in that they are not subject to a misalignment of the metal bumps with their underlying conductive pattern, and eliminate the need to use flux, thereby being environmentally friendly.

Claims

1. A method of manufacturing a semiconductor device package, said method comprising the steps of:

(A) forming a flexible circuit board by

(1) preparing a board comprising a polyimide tape having an upper surface and a lower surface, and Cu patterns plated with a Au layer attached to the lower surface of the polyimide tape,

(2) forming a plurality of via holes in the polyimide tape, which expose the Cu patterns to the upper surface of the polyimide tape,

(3) subsequently coating the upper surface of the polyimide tape with a photoresist, and exposing and developing the photoresist to form openings which expose the via holes,

(4) plating walls of the polyimide tape and of the photoresist which define the via holes and the openings, respectively, with Cu,

(5) subsequently removing remaining portions of the photoresist to produce bumps of the Cu which project above the upper surface of the polyimide tape, wherein shapes of the bumps correspond to shapes of the openings of the photoresist, respectively,

(6) plating the bumps of Cu to form plated bumps at the upper surface of the polyimide tape,

(7) removing an outer peripheral part of the polyimide tape located over portions of the Cu patterns at the lower surface of the polyimide tape to expose the portions of the Cu patterns, and

(8) etching the exposed portions of the Cu patterns off of the Au layer plated thereon to form metal leads comprising the Au layer;

(B) coating a lower surface of the flexible circuit board, corresponding to the lower surface of the polyimide tape, with an elastomer;

(C) after said step (B) of coating, attaching the lower surface of the flexible circuit board to an upper surface of a semiconductor chip;

(D) connecting the metal leads to chip pads of the semiconductor chip by cutting the metal leads adjacent an outermost part of the polyimide tape; and

(E) encapsulating the upper surface of the semiconductor chip and the metal leads.

2. A method of manufacturing a semiconductor device package as claimed in claim 1, wherein said step (A) (6) of plating comprises:

(6a) plating outer surfaces of the bumps of Cu with a layer of Ni; and

(6b) plating outer surfaces of the layer of Ni layer with a layer of Au.

3. A method of manufacturing a semiconductor device package as claimed in claim 1, wherein the bumps produced have a cylindrical shape corresponding to the shapes of the openings of the photoresist.