Method of fabricating a dual damascene structure

• US 6,042,996 A
• Filed: 04/13/1998
• Issued: 03/28/2000
• Est. Priority Date: 02/13/1998
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Benjamin Szu-Min, Chao, Fang-Ching
• Primary Examiner(s): Duda, Kathleen
• Application Number:
  US09/059,071
• Time in Patent Office: 715 Days
• Field of Search: 430/313, 430/314, 430/317, 430/323, 430/324, 430/396, 438/706, 216/17, 216/18, 216/49
• US Class Current: 430/313
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 2221/1021 Pre-forming the dual damascene structure in a resist layer

Abstract

A method of fabricating a dual damascene structure is provided comprising forming a photoresist layer on a dielectric layer. A mask including a region that light completely passes over, a region that light partially passes over and a dense region is used for exposure. A development step is carried out to remove the photoresist layer under the region that light completely passes over, to partially remove the photoresist layer under the region that light partially passes over and to leave the photoresist layer under the dense region. The photoresist layer remaining from the forgoing step and the dielectric layer are partially removed to form a via and a trench in the dielectric layer. The via and the trench are filled with metal to form a dual damascene structure.

Claims

1. A method of fabricating dual damascene structures, comprising the steps of:

providing a semiconductor substrate, wherein the semiconductor substrate has a plurality of devices and a dielectric layer on the devices;

forming a photoresist layer on the dielectric layer;

exposing the photoresist layer through a mask;

simultaneously etching the photoresist layer and the dielectric layer using an etchant to simultaneously form at least a trench and a via in the dielectric layer, wherein the via couples with one of the devices;

removing the photoresist layer remaining on the dielectric layer;

forming a conductive layer into the trench, the via and on the dielectric layer; and

partially removing the conductive layer to expose the surface of the dielectric layer.

2. A method according to claim 1, wherein the etching rate of the photoresist layer and the etching rate of the dielectric layer are about the same.

3. A method according to claim 1, wherein the mask comprises a transmissive region, a partially transmissive region, and an opaque region.

4. A method according to claim 3, wherein the opaque region of the mask is chromium.

5. A method according to claim 3, wherein the partially transmissive region is silicon-oxy nitride.

6. A method according to claim 3, wherein the partially transmissive region is chromic oxide.

7. A method according to claim 3, wherein the partially transmissive region is molybdic silicide.

8. A method according to claim 1, wherein the trench and the via are formed by anisotropic etching.

9. A method according to claim 1, wherein the conductive layer is a metal.

10. A method according to claim 1, wherein the step of partially removing the conductive layer is performed by chemical mechanical polishing.

11. A method of fabricating dual damascene structures, comprising the steps of:

providing a semiconductor substrate;

forming a plurality of devices on the semiconductor substrate;

forming a dielectric layer on the devices and the semiconductor substrate;

forming a photoresist layer on the dielectric layer;

exposing the photoresist layer through a mask, wherein the mask comprises a transmissive region, a partially transmissive region and an opaque region;

forming a first region of the photoresist layer under the transmissive region, forming a second region of the photoresist layer under the partially transmissive region and forming a third region of the photoresist layer under the opaque region;

simultaneously etching the photoresist layer and the dielectric layer to simultaneously form at least a via coupling with one of the devices and a trench in the dielectric layer by etching the dielectric layer through the photoresist layer;

removing the photoresist layer remaining on the dielectric layer;

forming a conductive layer over the substrate to fill the via and the trench; and

partially removing the conductive layer to expose the surface of the dielectric layer.

12. A method according to claim 11, wherein the etching rate of the photoresist layer and the etching rate of the dielectric layer are about the same.

13. A method according to claim 11, wherein the opaque region of the mask is chromium.

14. A method according to claim 11, wherein the partially transmissive region is silicon-oxy nitride.

15. A method according to claim 11, wherein the partially transmissive region is chromic oxide.

16. A method according to claim 11, wherein the partially transmissive region is molybdic silicide.

17. A method according to claim 11, wherein the trench and the via are formed by anisotropic etching.

18. A method according to claim 11, wherein the conductive layer is a metal.

19. A method according to claim 11, wherein the step of partially removing the conductive layer is performed by chemical mechanical polishing.