Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation
First Claim
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1. A method for fabricating a first memory cell and a second memory cell electrically isolated from each other, comprising the steps of:
- forming a first polysilicon (poly I) layer on an oxide coated substrate;
forming a sacrificial oxide layer over the poly I layer;
masking the poly I layer and sacrificial oxide layer to pattern floating gates of the first memory cell and the second memory cell and an unmasked portion therebetween;
transforming the unmasked portion of the poly I layer into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell;
forming an interpoly dielectric layer over the floating gates and insulator; and
forming a second polysilicon (poly II) layer over the interpoly dielectric layer.
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Abstract
A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.
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Citations
17 Claims
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1. A method for fabricating a first memory cell and a second memory cell electrically isolated from each other, comprising the steps of:
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forming a first polysilicon (poly I) layer on an oxide coated substrate; forming a sacrificial oxide layer over the poly I layer; masking the poly I layer and sacrificial oxide layer to pattern floating gates of the first memory cell and the second memory cell and an unmasked portion therebetween; transforming the unmasked portion of the poly I layer into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell; forming an interpoly dielectric layer over the floating gates and insulator; and forming a second polysilicon (poly II) layer over the interpoly dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for fabricating a first memory cell and a second memory cell electrically isolated from each other, comprising the steps of:
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forming a first polysilicon (poly I) layer on an oxide coated substrate; forming a sacrificial oxide layer and nitride layer for masking the poly I layer; etching at least a portion of the masking layer to pattern the first memory cell and the second memory cell and an unmasked portion therebetween; transforming the unmasked portion of the poly I layer into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell; and forming an interpoly dielectric layer and a second polysilicon (poly II) layer over the insulator and floating gates, the interpoly dielectric layer and a second polysilicon (poly II) layer being substantially free of abrupt changes in step height.
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14. A method for electrically isolating a first semiconductor structure from a second semiconductor structure, comprising the steps of:
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forming a polysilicon layer on an oxide coated substrate; forming a sacrificial oxide layer over the poly I layer; masking the polysilicon layer and the sacrificial oxide layer with a nitride mask to pattern the first semiconductor structure, the second semiconductor structure and an unmasked portion between the structures; partially etching the unmasked portion of polysilicon layer prior to a thermal oxidation step to compensate for at least one of lateral and vertical spreading of the insulator as compared to a thickness of the polysilicon layer; and transforming the unmasked portion of the polysilicon layer into an insulator via the thermal oxidation step such that the insulator electrically isolates the first semiconductor structure from the second semiconductor structure. - View Dependent Claims (15, 16, 17)
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Specification
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Current AssigneeMonterey Research, LLC (Vector Capital Corporation)
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Original AssigneeAdvanced Micro Devices, Inc.
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InventorsEarly, Kathleen R., Templeton, Michael K., Tripsas, Nicholas H., Chan, Maria C.
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Primary Examiner(s)BOOTH, RICHARD A
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Application NumberUS09/033,723Time in Patent Office756 DaysField of Search438/257-267, 438/294, 438/295US Class Current438/257CPC Class CodesH10B 41/30 characterised by the memory...
