Three-dimensional non-volatile memory

• US 6,043,122 A
• Filed: 06/16/1999
• Issued: 03/28/2000
• Est. Priority Date: 08/01/1995
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Liu, Yowjuang W., Haddad, Sameer S.
• Primary Examiner(s): Chang, Joni
• Application Number:
  US09/334,393
• Time in Patent Office: 286 Days
• Field of Search: 438/257, 438/258, 438/270, 438/268
• US Class Current: 438/257
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A strip of a semiconductor material (for example, P type silicon) is oxidized and the resulting strip of oxide is removed leaving a depression in the upper surface of the semiconductor material which has steep sidewalls. The steep sidewalls do not have significant ion impact damage because they are formed by oxidation and not by reactive ion etching of the semiconductor material. A high quality tunnel oxide can therefore be grown on the steep sidewalls. Floating gates are then formed on the tunnel oxide, corresponding word lines are formed over the floating gates, a conductive region (for example, N type silicon) is formed into the bottom of the depression, and a number of conductive regions (for example, N type silicon) corresponding with the floating gates are formed above the rim of the depression. The resulting bit transistors have channel regions which extend in a vertical dimension under floating gates along the surface of the sidewall. Because the depth and profile of the depression is determined primarily by oxidation and not by lithography, very small geometry bit transistors can be made.

Claims

1. A method of forming a non-volatile memory structure having a floating gate, the method comprising:

forming a depression into a semiconductor material by oxidizing a selected portion of a surface of a semiconductor material and then removing oxide from said depression, said depression having a sidewall; and

forming said floating gate of said non-volatile memory structure over said sidewall, said floating gate being insulated from said sidewall.

2. The method of claim 1, wherein said forming said depression involves removing substantially all oxide from said depression such that said sidewall is exposed.

3. The method of claim 1, further comprising:

after said forming a depression and before said forming said floating gate, oxidizing said sidewall to form a thin oxide layer over and in direct with said sidewall.

4. The method of claim 1, wherein said oxide which is removed from said depression has a thickness in a range of 1500 to 6000 angstroms.

5. The method of claim 1, wherein said sidewall is substantially free of ion impact damage.

6. The method of claim 1, wherein said depression is formed without reactive ion etching of the semiconductor material.