Method of fabricating vertical power MOSFET having low distributed resistance

• US 6,043,125 A
• Filed: 11/10/1997
• Issued: 03/28/2000
• Est. Priority Date: 12/30/1994
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Kasem, Mohammad, Williams, Richard K.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/966,553
• Time in Patent Office: 869 Days
• Field of Search: 438/270, 438/273, 438/274, 438/268, 438/269, 438/271, 438/272, 438/589, 438/138, 438/614, 438/612
• US Class Current: 438/270
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05118 Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/4846 with multiple bonds on the same bonding area
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/48644 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48655 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/48744 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48755 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/49111 : the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 23/4824 : Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 29/41741 : for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/73 : Bipolar junction transistors
• CPC Class Codes: H01L 29/7395 : Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer.

Claims

1. A method of fabricating a vertical current flow device in a semiconductor die, said method comprising the steps of:

forming an array of vertical transistor cells in said die, each of said cells being bordered by a control element and having a semiconductor region of a first conductivity adjacent a top surface of said die, said control element being disposed in a substrate of said die;

depositing a first metal layer over said die to a thickness of from 0.8 to 2.8 microns, said first metal layer being in electrical contact with said semiconductor regions;

depositing a passivation layer over said first metal layer;

etching an opening in said passivation layer so as to create an exposed area of said first metal layer over said device cells, wherein said step of etching an opening leaves a portion of said first metal layer along a perimeter of said exposed area covered by said passivation layer;

depositing a zinc layer on said exposed area and on at least a portion of said passivation layer;

depositing a nickel layer on said zinc layer;

forming a second metal layer to a thickness of at least 10 microns such that said second metal layer is in electrical contact with said exposed area of said first metal layer, said second metal layer being formed by electroless plating and being relatively thick compared to said first metal layer;

forming a gold layer on said second metal layer to a thickness from 0.1 to 0.3 microns.

2. The method of claim 1 comprising the step of etching a second opening in said passivation layer for a gate bonding pad.

3. The method of claim 1 wherein said step of etching an opening in said passivation layer further comprises etching an opening using a reactive ion etch.

4. The method of claim 1 further comprising a step of degreasing said exposed area after said step of etching an opening in said passivation layer.

5. The method of claim 4 wherein said step of degreasing further comprises degreasing with tricholoroethane.