Process for manufacture of MOS gated device with self aligned cells

• US 6,043,126 A
• Filed: 10/22/1997
• Issued: 03/28/2000
• Est. Priority Date: 10/25/1996
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kinzer, Daniel M.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/956,062
• Time in Patent Office: 888 Days
• Field of Search: 438/299, 438/268, 438/270, 438/273, 438/274, 438/303, 438/305, 438/589, 438/138, 438/527, 438/529, 148/DIG. 126
• US Class Current: 438/273
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66393 Lateral or planar thyristors
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7436 Lateral thyristors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

An MOS-gated power semiconductor device is formed by a process in which a self-aligned device cell is formed without any critical alignments. A sidewall spacer is used to mask the etching of a depression in the silicon to reduce the number of critical alignment steps. An optional selectively formed metal connects the polysilicon layer to the P+ and N+ diffusion regions. The sidewall spacer, in combination with the selectively formed metal, prevents impurities from diffusing to the parasitic DMOS channels and inverting them to cause leakage. A termination structure may also be formed by this process.

Claims

1. A process for fabricating a semiconductor device, said process comprising the steps of:

forming a layer of gate insulation material atop a silicon substrate of one conductivity type;

depositing a layer of polysilicon atop said layer of gate insulation material;

depositing a first overlaying insulation layer;

patterning and etching away selected regions of said first overlaying insulation layer to form a plurality of spaced openings therein which expose underlying regions of said layer of polysilicon;

etching away said underlying regions of said layer of polysilicon to form a further plurality of spaced openings therein;

introducing impurities of another conductivity type, which is of opposite conductivity type to said one conductivity type, into surface regions of said silicon substrate located beneath said further openings in said layer of polysilicon to form first diffused regions;

introducing impurities of said one conductivity type into said surface regions of said silicon substrate to form second diffused regions;

introducing impurities of said another conductivity type into said surface regions of said silicon substrate to form third diffused regions;

said second diffused regions having a final depth that is less than that of said third diffused regions, said first diffused regions being deeper and wider than and having a lower concentration than that of said third diffused regions;

depositing a second overlaying insulation layer subsequent to forming said first, second, and third diffused regions;

etching away a portion of said second overlaying insulation layer that is atop said first overlaying insulation layer, thereby leaving a remaining portion of second overlaying insulation layer that forms vertical sidewall spacers along sidewalls in each of said openings in said first overlaying insulation layer and along sidewalls in each of said further openings in said layer of polysilicon and which exposes a portion of each of said surface regions of said silicon substrate;

etching depressions in said exposed portion of said surface regions of said silicon substrate using said vertical sidewall spacers as a mask, said depressions being etched to a depth greater than the depth of said second diffused regions;

depositing a contact conductive layer; and

patterning and etching away portions of said contact conductive layer to form at least one source contact which contacts said second and third diffused regions and at least one gate contact.

2. The process of claim 1 further comprising the steps of:

depositing another conductive layer prior to depositing said contact conductive layer;

thermally treating said another conductive layer such that portions of said another conductive layer that contact said second and third diffused regions form a metal silicide layer that provides an electrical connection between said second and third diffused regions; and

removing unreacted portions of said another conductive layer.

3. The process of claim 2 further comprising the step of patterning and etching away a portion of said vertical sidewall spacers of said second overlaying insulation layer and a portion of said first overlaying insulation layer prior to said step of depositing another conductive layer;

and wherein said step of thermally treating said another conductive layer forms further portions of said metal silicide layer that contact said polysilicon layer and which provide an electrical connection between said polysilicon layer and said second and third diffused regions.

4. The process of claim 1 wherein said steps of introducing impurities of said one and another conductivity type includes implanting said impurities, into said silicon substrate through said layer of gate insulation material and then driving in said impurities.

5. The process of claim 1 wherein said one conductivity type is N-type and said another conductivity type is P-type.

6. The process of claim 1 wherein said first overlaying insulation layer comprises one of a thermally grown oxide, a low temperature oxide, a plasma enhanced chemical vapor deposited oxide, a plasma enhanced chemical vapor deposited TEOS and a furnace deposited TEOS.

7. The process of claim 1 wherein said second overlaying insulation layer comprises one of a furnace deposited TEOS layer, a low temperature oxide, a plasma enhanced chemical vapor deposited oxide and a plasma enhanced chemical vapor deposited TEOS.

8. The process of claim 2 wherein said another conductive layer is comprised of titanium.

9. The process of claim 2 wherein said step of thermally treating said another conductive layer includes rapid thermal annealing said another conductive layer at about 800°

C.

10. The process of claim 2 wherein said step of thermally treating said another conductive layer includes rapid thermal annealing said another conductive layer at about 600°

C. and then rapid thermal annealing said another conductive layer at about 800°

C.

11. The process of claim 1 wherein said step of depositing a layer of polysilicon further includes the steps of patterning and etching away selected regions of said polysilicon layer to form polysilicon diodes and then introducing impurities of said one conductivity type into said polysilicon layer.

12. The process of claim 1 further comprising the steps of:

forming a layer of field insulation material atop said silicon substrate;

patterning and etching away at least one selected region of said layer of field insulation material to form at least one opening in said layer of field insulation material and at least one remaining portion;

wherein said layer of gate insulation material is formed atop said silicon substrate in said at least one opening in said layer of field insulation material, said layer of polysilicon is formed atop said remaining portion of said layer of field insulation material and atop said layer of gate insulation material, said selected regions of said first overlaying insulation layer are etched away to form a plurality of first spaced openings therein which expose underlying regions of said layer of polysilicon which are atop said layer of gate insulation material and a plurality of second spaced openings which expose underlying regions of said layer of polysilicon which are atop said layer of field insulation material, said first underlying regions of said layer of polysilicon are further etched to form a further plurality of spaced openings therein, and said impurities of said another conductivity type are introduced into surface regions of said silicon substrate that are located beneath said further openings.

13. The process of claim 12 wherein said one conductivity type is N-type and said another conductivity type is P-type.

14. The process of claim 2 wherein said another conductive layer is comprised of tungsten.

15. The process of claim 1 wherein said step of depositing a contact conductive layer includes depositing a solderable contact metal atop said contact conductive layer.

16. The process of claim 15 wherein said solderable contact metal comprises a trimetal that includes respective layers of titanium, nickel and silver.

17. The process of claim 12 wherein said step of patterning and etching away portions of said contact conductive layer includes forming a gate bus which contacts a portion of said layer of polysilicon that is atop said layer of field insulation material.

18. The process of claim 17 wherein said layer of field insulation material includes a second opening that borders said semiconductor device and forms a street region, said layer of polysilicon includes at least one polysilicon ring located atop said layer of field insulation material between said gate bus and said street region and held at a floating potential.

19. The process of claim 1 wherein said third diffused regions are formed after said depressions are etched by introducing said impurities of said another conductivity type into said portion of said surface regions of silicon substrate.

20. The process of claim 2 wherein said another conductive layer is deposited atop only a portion of said second and third diffused regions.