Process for manufacture of MOS gated device with self aligned cells
First Claim
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1. A process for fabricating a semiconductor device, said process comprising the steps of:
- forming a layer of gate insulation material atop a silicon substrate of one conductivity type;
depositing a layer of polysilicon atop said layer of gate insulation material;
depositing a first overlaying insulation layer;
patterning and etching away selected regions of said first overlaying insulation layer to form a plurality of spaced openings therein which expose underlying regions of said layer of polysilicon;
etching away said underlying regions of said layer of polysilicon to form a further plurality of spaced openings therein;
introducing impurities of another conductivity type, which is of opposite conductivity type to said one conductivity type, into surface regions of said silicon substrate located beneath said further openings in said layer of polysilicon to form first diffused regions;
introducing impurities of said one conductivity type into said surface regions of said silicon substrate to form second diffused regions;
introducing impurities of said another conductivity type into said surface regions of said silicon substrate to form third diffused regions;
said second diffused regions having a final depth that is less than that of said third diffused regions, said first diffused regions being deeper and wider than and having a lower concentration than that of said third diffused regions;
depositing a second overlaying insulation layer subsequent to forming said first, second, and third diffused regions;
etching away a portion of said second overlaying insulation layer that is atop said first overlaying insulation layer, thereby leaving a remaining portion of second overlaying insulation layer that forms vertical sidewall spacers along sidewalls in each of said openings in said first overlaying insulation layer and along sidewalls in each of said further openings in said layer of polysilicon and which exposes a portion of each of said surface regions of said silicon substrate;
etching depressions in said exposed portion of said surface regions of said silicon substrate using said vertical sidewall spacers as a mask, said depressions being etched to a depth greater than the depth of said second diffused regions;
depositing a contact conductive layer; and
patterning and etching away portions of said contact conductive layer to form at least one source contact which contacts said second and third diffused regions and at least one gate contact.
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Abstract
An MOS-gated power semiconductor device is formed by a process in which a self-aligned device cell is formed without any critical alignments. A sidewall spacer is used to mask the etching of a depression in the silicon to reduce the number of critical alignment steps. An optional selectively formed metal connects the polysilicon layer to the P+ and N+ diffusion regions. The sidewall spacer, in combination with the selectively formed metal, prevents impurities from diffusing to the parasitic DMOS channels and inverting them to cause leakage. A termination structure may also be formed by this process.
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Citations
20 Claims
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1. A process for fabricating a semiconductor device, said process comprising the steps of:
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forming a layer of gate insulation material atop a silicon substrate of one conductivity type; depositing a layer of polysilicon atop said layer of gate insulation material; depositing a first overlaying insulation layer; patterning and etching away selected regions of said first overlaying insulation layer to form a plurality of spaced openings therein which expose underlying regions of said layer of polysilicon; etching away said underlying regions of said layer of polysilicon to form a further plurality of spaced openings therein; introducing impurities of another conductivity type, which is of opposite conductivity type to said one conductivity type, into surface regions of said silicon substrate located beneath said further openings in said layer of polysilicon to form first diffused regions; introducing impurities of said one conductivity type into said surface regions of said silicon substrate to form second diffused regions; introducing impurities of said another conductivity type into said surface regions of said silicon substrate to form third diffused regions;
said second diffused regions having a final depth that is less than that of said third diffused regions, said first diffused regions being deeper and wider than and having a lower concentration than that of said third diffused regions;depositing a second overlaying insulation layer subsequent to forming said first, second, and third diffused regions; etching away a portion of said second overlaying insulation layer that is atop said first overlaying insulation layer, thereby leaving a remaining portion of second overlaying insulation layer that forms vertical sidewall spacers along sidewalls in each of said openings in said first overlaying insulation layer and along sidewalls in each of said further openings in said layer of polysilicon and which exposes a portion of each of said surface regions of said silicon substrate; etching depressions in said exposed portion of said surface regions of said silicon substrate using said vertical sidewall spacers as a mask, said depressions being etched to a depth greater than the depth of said second diffused regions; depositing a contact conductive layer; and patterning and etching away portions of said contact conductive layer to form at least one source contact which contacts said second and third diffused regions and at least one gate contact. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification