Bottom lead semiconductor chip package

• US 6,043,430 A
• Filed: 02/13/1998
• Issued: 03/28/2000
• Est. Priority Date: 03/14/1997
• Status: Expired due to Term

• Current Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Original Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Inventors: Chun, Heung-Sup
• Primary Examiner(s): Kincaid, Kristine
• Assistant Examiner(s): Ngo, Hung V
• Application Number:
  US09/023,287
• Time in Patent Office: 774 Days
• Field of Search: 257/672, 257/686, 257/693, 257/735, 257/685, 257/777, 257/673, 174/52.2, 174/52.4
• US Class Current: 174/530
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor

Abstract

A bottom lead package is capable of increasing a memory capacity for a mounting position on a mother board by stacking several semiconductor packages such that exposed surfaces of leads on upper and lower surfaces of the package are aligned. The package includes a semiconductor chip, a plurality of lower leads attached to the lower side of the chip by an adhesive, a plurality of upper leads attached to the upper side of the chip by an adhesive and to the upper surfaces of the lower leads, wherein metal wires electrically connect the upper leads with a plurality of chip pads formed on the chip, and wherein a molding section packages the chip, the metal wires and the upper and lower leads, such that the upper and lower surfaces of the upper and lower leads, respectively, are externally exposed.

Claims

1. A chip package, comprising:

a chip;

a plurality of lower leads that are attached to a lower side of the chip;

a plurality of upper leads that are attached to an upper side of the chip and that are connected to corresponding ones of the lower leads;

a plurality of conductive media that couple ones of the upper and lower leads with corresponding ones of a plurality of chip pads formed on the chip; and

a molding section packaging the chip, the conductive media and the upper and lower leads such that upper and lower surfaces of the upper and lower leads, respectively, are externally exposed.

2. The package of claim 1, wherein said plurality of conductive media comprise metal wires made of Au.

3. The package of claim 1, wherein said plurality of lower leads are attached to the chip via an insulating adhesive.

4. The package of claim 1, wherein said plurality of upper leads are attached to the upper side of the chip by an insulating adhesive.

5. The package of claim 1, wherein said plurality of upper leads are attached to corresponding chip pads of the chip via the plurality of conductive media.

6. The package of claim 5, wherein the plurality of conductive media comprise one of solder bumps and solder balls.

7. The package of claim 1, wherein the plurality of upper leads are connected to respective ones of the plurality of lower leads by a conductive adhesive.

8. The chip package of claim 1, wherein corresponding ones of said plurality of lower and upper leads are rigidly attached to one another and formed to act as monolithic units.

9. A chip package, comprising:

a chip;

a plurality of leads, wherein each lead has a first portion that extends above an upper surface of the chip, a middle portion, and a second portion that extends below a bottom surface of the chip, and wherein the first portions of the leads are attached to the upper surface of the chip and the second portions of the leads are attached to a bottom surface of the chip;

a plurality of conductive media that couple ones of a plurality of chip pads on the chip to corresponding ones of the plurality of leads; and

a molding section that packages the chip, the plurality of leads and the plurality of conductive media such that only surfaces of the first portions of the leads and surfaces of the second portions of the leads are externally exposed.

10. The chip package of claim 9, wherein the first portions of the leads are attached to the chip pads of the chip by the plurality of conductive media.

11. The chip package of claim 10, wherein the plurality of conductive media are one of solder balls and solder bumps.

12. The chip package of claim 9, wherein the plurality of conductive media comprise electrically conductive wires.

13. The chip package of claim 9, wherein lower surfaces of the first portions of the leads are attached to the upper surface of the chip by an insulating adhesive.