High speed CMOS photodetectors with wide range operating region

• US 6,043,525 A
• Filed: 12/15/1998
• Issued: 03/28/2000
• Est. Priority Date: 04/07/1997
• Status: Expired due to Fees

• Current Assignee: Pao-Jung Chen
• Original Assignee: Pao-Jung Chen
• Inventors: Chen, Pao-Jung
• Primary Examiner(s): Ngo , Ngan V.
• Application Number:
  US09/212,878
• Time in Patent Office: 469 Days
• Field of Search: 257/291, 257/292, 257/461, 250/215, 327/514, 327/515
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A CMOS charge-integration mode photo-detector built on an n-type substrate is disclosed in this invention. This photo-detector includes a p+n photodiode with the n-type substrate constituting an n-region and a p+ diffusion region disposed near a top surface of the n-type substrate, the p+ diffusion region constituting a charge integration node. The photodetector further includes a gate-biased charge storable n-type MOS transistor functioning as a photo-conversion voltage amplifier supported on the substrate formed with a threshold voltage of Vt0 having a gate terminal connected to the charge-integration node. The photodetector further includes a MOS transistor supported on the substrate functioning as a constant current-source load transistor having a drain terminal connected to a source terminal of the gate-biased charge storable n-type MOS transistor and a gate terminal connected to a bias reference voltage. The photodetector further includes a pre-charge switch transistor supported on the substrate having a source terminal connected to charge-integration node and a drain terminal connected to a bias voltage source. In an alternate preferred embodiment, the photo-detector is formed in a p-type substrate.

Claims

1. A CMOS photo-detector supported on a substrate comprising:

a p-n junction diode having a charge-integration node;

a gate-biased charge storable MOS transistor having a gate terminal connected to the charge-integration node of said p-n junction diode;

a constant current-source load MOS transistor having a drain terminal connected to a source terminal of said charge storable MOS transistor, and a gate terminal connected to a reference voltage V_biasI ;

a bias charge pre-switch transistor connected to said charge-integration node responsive to a control signal for providing a source of voltage reference as a pre-charge bias voltage V_bias to said gate terminal of said gate-biased charge storable MOS transistor.

2. The photo-detector of claim 1 wherein:

said substrate is an N-type substrate and said constant current-source load MOS transistor is NMOS transistor.

3. The photo-detector of claim 1 wherein:

said substrate is a P-type substrate and said constant current-source load MOS transistor is PMOS transistor.

4. The photo-detector of claim 2 wherein:

said constant current-source load MOS transistor is a depletion type MOS transistor for providing a negative threshold voltage.

5. The photo-detector of claim 1 further comprising:

a sample and hold capacitor amplifier circuit having a terminal connected to said source terminal of said charge storable MOS transistor for receiving and holding an output signal, and a sampling-and-hold readout switch transistor for outputting said output signal.

6. The photo-detector of claim 1 further comprising:

a first sample and hold capacitor amplifier circuit having a terminal connected to the said source terminal of said charge storable MOS transistor for receiving and holding an output signal, and a sampling-and-hold readout switch transistor for outputting said output signal; and

a second sample and hold capacitor amplifier circuit having a terminal connected to the said source terminal of said charge storable MOS transistor for receiving and holding an output signal, and a sampling-and-hold readout switch transistor for outputting said output signal.

7. The photo-detector of claim 1 further comprising:

a buffer source-follower MOS transistor having a gate terminal connected to said source terminal of said gate-biased charge storable MOS transistor of said photo-detector; and

a readout switch MOS transistor having a drain terminal connected to a source terminal of said buffer source-follower MOS transistor and a gate terminal connected to a second control signal S₂ for outputting photo-signals of said photo-detector.

8. The photo-detector of claim 1 further comprising:

an on-off switch MOS transistor having a drain terminal connected to a source terminal of said constant current-source load MOS transistor of said photo-detector, and a source terminal connected to a ground bus, and a gate terminal connected to a power enabling control signal S_PE for enabling and disabling the current of said current-source load MOS transistor.

9. The photo-detector of claim 1 further comprising:

a readout switch MOS transistor having a drain terminal connected to a source terminal of said buffer source-follower MOS transistor and a gate terminal connected to a second control signal S₂ for outputting photo-signals of said photo-detector; and

a resetable capacitor and current-source load amplifier having a terminal connected to a source terminal of said readout switch transistor for receiving an output signal, and an output amplifier transistor for outputting said output signal.

10. The photo-detector of claim 9 wherein:

said resetable capacitor and current-source load amplifier comprising a capacitor having a cathode node connected to ground bus, and a anode node connected to a source terminal of said readout switch MOS transistor of said photo-detector;

a second constant current-source load MOS transistor having a drain terminal connected to a anode of said capacitor, and a source terminal connected to ground bus, and a gate terminal connected to a second reference voltage V'"'"'_biasI ;

a capacitor reset switch MOS transistor having a gate terminal connected to a third control signal in conjunction with said readout switch for outputting the output signal to said anode node of said capacitor; and

an output MOS transistor having a gate terminal connected to said anode node for receiving said output signal and a source terminal for outputting said output signal.

11. The photo-detector of claim 1 further comprising:

a buffer source-follower MOS transistor having a gate terminal connected to said source terminal of said gate-biased charge storable MOS transistor of said photo-detector; and

a second constant current-source load MOS transistor having a drain terminal connected to a source terminal of said buffer source-follower transistor, a source terminal connected to a ground bus, and a gate terminal connected to said reference voltage V_biasI.

12. A linear array of photo-detectors supported on a substrate wherein each of said photo-detectors comprising:

a p-n junction diode having a charge-integration node;

a gate-biased charge storable MOS transistor having a gate terminal connected to the charge-integration node of said p-n junction diode;

a constant current-source load MOS transistor having a drain terminal connected to a source terminal of said charge storable MOS transistor, and a gate terminal connected to a reference voltage V_biasI ;

a bias charge pre-charge switch transistor connected to said charge-integration node responsive to a pre-charge control signal for providing a source of voltage reference as a pre-charge bias voltage V_bias to said gate terminal of said gate-biased charge storable MOS transistor;

a buffer source-follower MOS transistor having a gate terminal connected to said source terminal of said gate-biased charge storable MOS transistor of said photo-detector; and

a readout switch MOS transistor having a drain terminal connected to a source terminal of said buffer source-follower transistor and a gate terminal connected to a readout control signal for outputting photo-signals of said photo-detector.

13. The linear array of photo-detectors of claim 12 further comprising:

a digital scanning shift register having a plurality of bits each being connected to a gate terminal of each of said readout switch transistor for sequentially reading out a video signal detected by each of said photo-detectors, and connected to each of said bias charge pre-charge switch transistor for resetting to said voltage reference; and

a resetable capacitor and current-source load amplifier including a buffer amplifier connected to a common source terminal of said readout switch transistor for receiving an output signal sequentially from each of said photo-detectors.

14. A linear array of photo-detectors supported on a substrate wherein each of said photo-detectors comprising:

a p-n junction diode having a charge-integration node;

a gate-biased charge storable MOS transistor having a gate terminal connected to the charge-integration node of said p-n junction diode;

a constant current-source load transistor having a drain terminal connected to a source terminal of said charge storable MOS transistor, and a gate terminal connected to a reference voltage V_biasI ;

a bias charge pre-charge switch transistor connected to said charge-integration node responsive to a pre-charge control signal for providing a source of voltage reference as a pre-charge bias voltage V_bias to said gate terminal of said gate-biased charge storable MOS transistor; and

a sample and hold capacitor amplifier circuit having a terminal connected to the said source terminal of said charge storable MOS transistor for receiving and holding an output signal and a sampling-and-hold readout switch transistor for outputting said output signal.

15. A linear array of photo-detectors of claim 14 further comprising:

a digital scanning shift register having a plurality of bits each being connected to a gate terminal of each of said sample-and hold readout switch transistor for sequentially reading out a video signal detected by each of said photo-detectors; and

a resetable capacitor current-source load amplifier including a buffer amplifier connected to a common source terminal of said readout switch transistor of said sample-and-hold amplifiers for receiving an output signal sequentially from each of said photo-detectors.

16. A CMOS photodetector supported on a P-type substrate comprising:

a N⁺ P junction diode having a charge-integration node connected to a N⁺ terminal of said N⁺ P junction diode;

a gate-biased charge storable NMOS transistor having a gate terminal connected to the charge-integration node of said N⁺ junction diode;

a constant current-source load NMOS transistor having a drain terminal connected to a source terminal of said charge storable NMOS transistor, and a gate terminal connected to a reference voltage V_biasI ; and

a bias charge pre charge switch transistor connected to said charge-integration node responsive to a pre-charge control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable NMOS transistor.

17. The photo-detector of claim 16 further comprising:

a sample and hold capacitor amplifier circuit having a terminal connected to said source terminal of said charge storable MOS transistor for receiving and holding an output signal, and a sampling-and-hold readout switch transistor for outputting said output signal.

18. The photo-detector of claim 16 further comprising:

a first sample and hold capacitor amplifier circuit having a terminal connected to the said source terminal of said charge storable MOS transistor for receiving and holding an output signal, and a sampling-and-hold readout switch transistor for outputting said output signal; and

a second sample and hold switch and a sample and hold capacitor amplifier circuit having a terminal of said sample and hold switch connected to said source terminal of said gate-biased charge storable MOS transistor for receiving and holding an output signal, and a sampling-and-hold readout switch transistor for outputting said output signal.

19. The photo-detector of claim 16 further comprising:

a buffer source-follower MOS transistor having a gate terminal connected to said source terminal of said gate-biased charge storable MOS transistor of said photo-detector;

a current-source load MOS transistor having a drain terminal connected to a source terminal of said buffer source-follower transistor, a source terminal connected to a ground bus, and a gate terminal connected to said reference voltage V_biasI.

20. The photo-detector of claim 16 further comprising:

a buffer source-follower MOS transistor having a gate terminal connected to said source terminal of said gate-biased charge storable MOS transistor of said photo-detector;

a readout switch MOS transistor having a drain terminal connected to a source terminal of said buffer source-follower transistor and a gate terminal connected to a read-out control signal for outputting photo-signals of said photo-detector.

21. A CMOS photo-detector supported on a P-type substrate comprising:

a N⁺ P junction diode having a charge-integration node connected to a N⁺ terminal of said N⁺ P junction diode;

a gate-biased charge storable NMOS transistor having a gate terminal connected to the charge-integration node of said N⁺ P junction diode;

a readout switch transistor connected to a source terminal of said charge storable NMOS transistor; and

a bias charge pre-charge switch transistor connected to said charge-integration node responsive to a pre-charge control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable NMOS transistor.