Flash EEPROM device employing polysilicon sidewall spacer as an erase gate

• US 6,043,530 A
• Filed: 04/15/1998
• Issued: 03/28/2000
• Est. Priority Date: 04/15/1998
• Status: Expired due to Term

• Current Assignee: Ming-Bing Chang
• Original Assignee: Ming-Bing Chang
• Inventors: Chang, Ming-Bing
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US09/060,673
• Time in Patent Office: 713 Days
• Field of Search: 257/315, 257/316, 257/321, 257/320, 438/257, 365/185.02
• US Class Current: 257/320
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V_cc scaling becomes possible.

Claims

1. A Flash EEPROM cell structure comprising:

a body of semiconductor material having a substrate of a first conductivity type, a source region and a drain region each of a second conductivity type, and a channel region of the first conductivity type extending between the source region and the drain region;

a floating gate extending over a portion of the channel region with a thin insulator layer therebetween;

a control gate overlying the floating gate with an insulator layer therebetween, so as to form a stack gate, the stack gate located proximately to the source region; and

a conductive, sidewall-spacer erase gate insulated from the drain region and the stack gate, the erase gate located proximately to the drain region and insulated from the floating gate with a first thin dielectric layer therebetween, and insulated from the control gate with a second thin dielectric layer therebetween, the erase gate overlying a portion of the substrate and presenting a spacer width substantially along the channel region, the erase gate also insulated from the portion of the substrate with a third thin dielectric layer therebetween,

wherein the first thin dielectric layer is thinner than the second thin dielectric layer such that with proper biasing, electron tunneling is possible between the erase gate and the floating gate and wherein the thickness of the second thin dielectric layer is such that with proper biasing, substantially no electron leakage is possible between the erase gate and the control gate.

2. A Flash EEPROM cell as in claim 1 wherein the first thin dielectric layer presents a thickness between 50 Å

and 250 Å

.

3. A Flash EEPROM cell as in claim 1 wherein the second thin dielectric layer is thicker than the first thin dielectric layer and presents a thickness between 200 Å

and 500 Å

.

4. A Flash EEPROM array having a plurality of sectors, each sector having a plurality of rows and a plurality of columns of cells, and each cell comprising:

a body of semiconductor material having a substrate of a first conductivity type, a source region and a drain region each of a second conductivity type, and a channel region of the first conductivity type extending between the source region and the drain region;

a floating gate extending over a portion of the channel region with a thin insulator layer therebetween;

a control gate overlying the floating gate with an insulator layer therebetween, so as to form a stack gate, the stack gate located proximately to the source region; and

a conductive, sidewall-spacer erase gate insulated from the drain region and the stack gate, the erase gate located proximately to the drain region and insulated from the floating gate with a first thin dielectric layer therebetween, and insulated from the control gate with a second thin dielectric layer therebetween, the erase gate overlying a portion of the substrate and presenting a spacer width substantially along the channel region, the erase gate also insulated from the portion of the substrate with a third thin dielectric layer therebetween,

wherein the first thin dielectric layer is thinner than the second thin dielectric layer such that with proper biasing, electron tunneling is possible between the erase gate and the floating gate, wherein the thickness of the second thin dielectric layer is such that with proper biasing, substantially no electron leakage is possible between the erase gate and the control gate, and wherein each erase gate is electrically connected to all other erase gates within the sector.

5. The Flash EEPROM array of claim 4 wherein the sector size is two rows of cells.

6. The Flash EEPROM array of claim 4 wherein the sector size is 1024 rows of cells.

7. The Flash EEPROM array as in claim 4 wherein each sector can be further divided into a plurality of blocks, each block having a plurality of rows of cells, wherein each erase gate of a given block is electrically only connected to all other erase gates within the block.

8. A Flash EEPROM cell structure comprising:

a body of semiconductor material having a substrate of a first conductivity type, a source region and a drain region each of a second conductivity type, and a channel region of the first conductivity type extending between the source region and the drain region;

a floating gate extending over a portion of the channel region with a thin insulator layer therebetween;

a control gate overlying the floating gate with an insulator layer therebetween, so as to form a stack gate, the stack gate located proximately to the drain region; and

a conductive, sidewall-spacer erase gate insulated from the source region and the stack gate, the erase gate located proximately to the source region and insulated from the floating gate with a first thin dielectric layer therebetween, and insulated from the control gate with a second thin dielectric layer therebetween, the erase gate overlying a portion of the substrate and presenting a spacer width substantially along the channel region, the erase gate also insulated from the portion of the substrate with a third thin dielectric layer therebetween,

wherein the first thin dielectric layer is thinner than the second thin dielectric layer such that with proper biasing, electron tunneling is possible between the erase gate and the floating gate and wherein the thickness of the second thin dielectric layer is such that with proper biasing, substantially no electron leakage is possible between the erase gate and the control gate.

9. A Flash EEPROM cell as in claim 8 wherein the first thin dielectric layer presents a thickness between 50 Å

and 250 Å

.

10. A Flash EEPROM cell as in claim 8 wherein the second thin dielectric layer is thicker than the first thin dielectric layer and presents a thickness between 200 Å

and 500 Å

.

11. A Flash EEPROM array having a plurality of sectors, each sector having a plurality of rows and a plurality of columns of cells, and each cell comprising:

a body of semiconductor material having a substrate of a first conductivity type, a source region and a drain region each of a second conductivity type, and a channel region of the first conductivity type extending between the source region and the drain region;

a floating gate extending over a portion of the channel region with a thin insulator layer therebetween;

a control gate overlying the floating gate with an insulator layer therebetween, so as to form a stack gate, the stack gate located proximately to the drain region; and

a conductive, sidewall-spacer erase gate insulated from the source region and the stack gate, the erase gate located proximately to the source region and insulated from the floating gate with a first thin dielectric layer therebetween, and insulated from the control gate with a second thin dielectric layer therebetween, the erase gate overlying a portion of the substrate and presenting a spacer width substantially along the channel region, the erase gate also insulated from the portion of the substrate with a third thin dielectric layer therebetween,

wherein the first thin dielectric layer is thinner than the second thin dielectric layer such that with proper biasing, electron tunneling is possible between the erase gate and the floating gate, wherein the thickness of the second thin dielectric layer is such that with proper biasing, substantially no electron leakage is possible between the erase gate and the control gate, and wherein each erase gate is electrically connected to all other erase gates within the sector and each source is electrically connected to all other sources within the sector.