Method and integrated circuit structure for preventing latch-up in CMOS integrated circuit devices
First Claim
1. An integrated circuit structure, comprising:
- a semiconductor substrate of a material of a first conductivity type wherein said substrate includes at least a first doped portion heavily doped by a material of said first conductivity type;
a well region in said substrate, said well region including a first doped portion heavily doped by a material of a second conductivity type, and a second doped portion lightly doped by a material of said second conductivity type;
a first metal conductor electrically connected to said first doped portion of said well region for connecting said first doped portion to a first pumped voltage source;
a second metal conductor electrically coupled to said second doped portion of said well region for connecting said well region to a second voltage source, the first pumped voltage source being greater in potential than the second voltage source;
a third metal conductor electrically coupled to first doped portion of said substrate and connected to a third voltage source; and
a Schottky rectifying junction fabricated in said lightly doped portion of said well region, said second voltage source being coupled to said first pumped voltage source through a path including said rectifying Schottky junction.
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Abstract
An integrated circuit structure for preventing latch-up of an integrated circuit device, such as a dynamic random access memory, that is operated with a negative substrate bias in use of the device. The integrated circuit structure includes a p-type substrate having an n-well region formed therein, with a rectifying junction formed in a lightly doped portion of the n-well region and connected to provide a path to ground for clamping the substrate to ground during power-up conditions. In another embodiment, a rectifying junction formed in a lightly doped portion of the n-well region functions as a diode clamp for a pumped bias voltage for the n-well region. In forming the rectifying junction in the n-well region, the n-plus ion implantation mask that is used in forming n-plus doped regions in the n-well region is used to mask portions of the n-well region during the n-plus ion implantation process and a metal barrier layer is formed on the exposed lightly doped portions of the n-well region, so that a Schottky diode is formed. Also described is a method for fabricating an integrated circuit structure which includes forming a rectifying junction in the well portion for providing a diode clamp between voltage sources of the integrated circuit structure.
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Citations
11 Claims
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1. An integrated circuit structure, comprising:
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a semiconductor substrate of a material of a first conductivity type wherein said substrate includes at least a first doped portion heavily doped by a material of said first conductivity type; a well region in said substrate, said well region including a first doped portion heavily doped by a material of a second conductivity type, and a second doped portion lightly doped by a material of said second conductivity type; a first metal conductor electrically connected to said first doped portion of said well region for connecting said first doped portion to a first pumped voltage source; a second metal conductor electrically coupled to said second doped portion of said well region for connecting said well region to a second voltage source, the first pumped voltage source being greater in potential than the second voltage source; a third metal conductor electrically coupled to first doped portion of said substrate and connected to a third voltage source; and a Schottky rectifying junction fabricated in said lightly doped portion of said well region, said second voltage source being coupled to said first pumped voltage source through a path including said rectifying Schottky junction. - View Dependent Claims (2, 3)
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4. An integrated circuit structure, comprising:
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a semiconductor substrate of a p-type material, said substrate including a p-doped portion formed by a material having a heavy p-plus concentration; a well region of an n-type material in said substrate, said well region defining a lightly n-doped portion and including at least one heavily n-doped portion formed by a material having a heavy n-plus concentration; a first metal conductor electrically connected to said p-doped portion for coupling said substrate to a source of a negative substrate bias voltage; a second metal conductor electrically connected to said heavily n-doped portion for coupling said n-well region to a source of a pumped potential; a Schottky rectifying junction in said n-well region; and a third metal conductor electrically connected to said rectifying junction and to the pumped potential through a path including said Schottky rectifying junction. - View Dependent Claims (5, 6, 7)
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8. An integrated circuit structure, comprising:
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a semiconductor substrate of a p-type material wherein said substrate includes at least a first p-doped portion heavily doped by a material having a heavy p-plus concentration; an n-type well region in said substrate, said well region including a first n-doped portion heavily doped by a material having a heavy n-plus concentration, and a second lightly n-doped portion; a first metal conductor electrically connected to said first n-doped portion of said well region for connecting said first n-doped portion to a first pumped voltage source; a second metal conductor electrically coupled to said second lightly n-doped portion of said well region for connecting said well region to a second voltage source, the first pumped voltage source being greater in potential than the second voltage source; a third metal conductor electrically coupled to the first p-doped portion of said substrate and connected to a third voltage source; and a Schottky rectifying junction fabricated in said lightly n-doped portion of said well region, said second voltage source being coupled to said first pumped voltage source through a path including said rectifying Schottky junction.
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9. An integrated circuit, comprising:
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a semiconductor substrate of a material of a first conductivity type having a heavily doped portion of the first conductivity type; a well region of a second conductivity type formed in the semiconductor substrate, including a heavily doped portion of the second conductivity type; a first conductor for coupling the heavily doped portion of the semiconductor substrate to a source of a bias voltage; a second conductor for coupling the heavily doped portion of the well region to a reference potential; a rectifying junction in the well region, the substrate coupled to the reference potential through a path including the rectifying junction.
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10. A dynamic random access memory (DRAM), comprising:
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an array of memory cells formed on a substrate; and a rectifying junction for clamping the substrate to a reference potential to prevent forward biasing of parasitic junctions in the DRAM.
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11. An integrated circuit structure, comprising:
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a semiconductor substrate of a p-type material wherein said substrate includes at least a first p-doped portion heavily doped by a material having a heavy p-plus concentration; an n-type well region in said substrate, said well region including a first n-doped portion heavily doped by a material having a heavy n-plus concentration, and a second lightly n-doped portion; a first metal conductor connected to said first doped portion of said well region by a metal plug, the first conductor for connecting said first doped portion to a first pumped voltage source; a second metal conductor coupled to said second doped portion of said well region by a second metal plug, the second conductor for connecting said well region to a second voltage source, the first pumped voltage source being greater in potential than the second voltage source; a third metal conductor electrically coupled to the first p-doped portion of said substrate by a third metal plug and connected to a back bias voltage source; and a Schottky rectifying junction fabricated in said lightly n-doped portion of said well region, said second voltage source being coupled to said first pumped voltage source through a path including said rectifying Schottky junction.
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Specification