Power factor correction method and apparatus

• US 6,043,633 A
• Filed: 06/05/1998
• Issued: 03/28/2000
• Est. Priority Date: 06/05/1998
• Status: Expired due to Term

• Current Assignee: S.t.l. Energy Solutions And Technologies Ltd.
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG), Systel Development and Industries Limited
• Inventors: Rubin, Daniel, Lev, Arie, Kalichstein, Moshe, Sharaby, Yoel
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US09/092,270
• Time in Patent Office: 662 Days
• Field of Search: 323/282, 323/283, 323/284, 323/285, 323/222, 323/223, 363/60
• US Class Current: 323/222
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A method and apparatus for controlling a boost converter, which offers improved power factor correction by compensating for the distorting effects of parasitic capacitance and parasitic oscillations. By precise adjustments to the closing time of the boost switch, the effects of parasitic capacitance can be reduced or eliminated. A zero current detector capable of detecting both forward and reverse zero current points facilitates the compensation. The method and circuit of the present invention are well-suited to integration with an inexpensive digital controller such as a microprocessor, and a method of dithering to enhance the time resolution of clocked digital circuits is presented.

Claims

1. A zero current detector for a boost converter, the boost converter including a boost switch with a first connection to an inductor having an inductor current, the zero current detector operative to detecting zero inductor current, the zero current detector comprising:

(a) a capacitor connected to the first connection;

(b) a first diode with a second connection to said capacitor and a third connection to the boost switch;

(c) a second diode connected to said second connection; and

(d) a zero current sense output point at said second connection.

2. The zero current detector as in claim 1, further operative to the detection of zero forward inductor current and zero reverse inductor current.

3. A method for controlling a boost converter for power factor correction, the boost converter having a boost switch and an inductor with an inductor current, the method comprising the steps of:

(a) providing a zero current detector operative to the detection of zero reverse inductor current; and

(b) closing the boost switch when said zero current detector detects said zero reverse inductor current.

4. A method for controlling a boost converter for power factor correction, the boost converter having a boost switch and an inductor current, the boost switch having an effective time interval for being closed, the method comprising the steps of:

(a) predetermining a minimum inductor current;

(b) providing a minimum current discriminator, said minimum current discriminator operative to determining that the inductor current is equal to said minimum inductor current;

(c) closing the boost switch;

(d) waiting until said minimum current discriminator determines that the inductor current is equal to said minimum inductor current;

(e) commencing the effective time interval;

(f) waiting for the completion of the effective time interval; and

(g) opening the boost switch.

5. A method for using a clocked digital circuit to generate a duty cycle for use in a pulse-width modulator for power factor correction, the clocked digital circuit operative to generating a plurality of discrete time intervals, the duty cycle having at least one state with an intermediate time interval distinct from any of the discrete time intervals generated by the clocked digital circuit, the method comprising the step of constructing a group of a plurality of time intervals selected from the plurality of discrete time intervals generated by the clocked digital circuit, such that the average of the time intervals of said group approximates the intermediate time interval.

6. A method for controlling a power converter having an inductor and a switching transistor, the switching transistor being coupled from one end of the inductor to a common voltage potential, the inductor having an inductor current capable of being substantially zero flowing in either direction, the method comprising the steps of:

(a) detecting when the inductor current increases from the reverse direction and reaches zero; and

(b) turning on the switching transistor.

7. A method for controlling a power converter for providing power factor correction, the power converter including an inductor having an inductor current and a stored inductor energy, and a switching transistor having a parasitic capacitance storing a parasitic capacitance energy, the switching transistor being coupled from one end of the inductor to a common voltage, the method comprising the steps of:

(a) determining a predetermined effective time interval during which the switching transistor should remain on to achieve a desired power factor correction;

(b) determining a minimum value for the inductor current which would result in the stored inductor energy being substantially equal to the parasitic capacitance energy;

(c) turning on the switching transistor;

(d) commencing a measurement of elapsed time when the inductor current reaches said minimum value; and

(e) turning off the switching transistor when said elapsed time substantially equals said predetermined effective time interval.

8. A method for controlling a duty cycle of a switching power converter using a clocked digital circuit driven by a digital clock having a fixed clock period, the method comprising the steps of:

(a) determining a desired duty cycle time period;

(b) determining a lower number of clock periods having a sum lower than said desired duty cycle time period;

(c) determining a higher number of clock periods having a sum higher than said desired duty cycle time period;

(d) adjusting the duty cycle of the switching power converter to have a first time period equal to the sum of the lower number of clock periods for a first number of cycles; and

(e) adjusting the duty cycle of the switching power converter to have a second time period equal to the sum of the higher number of clock periods for a second number of cycles,

wherein an average time period of said first number of cycles each having said first time period and said second number of cycles each having said second time period is substantially equal to said desired duty cycle time period.

9. A zero current detector for a power converter having an inductor and a switching transistor, the switching transistor being coupled from one end of the inductor having an inductor current to a common voltage, the zero current detector circuit comprising:

(a) a capacitor having a first end and a second end, said first end being coupled to the one end of the inductor;

(b) a first diode having a first anode and a first cathode, said first anode being coupled to the common voltage and said first cathode being coupled to said second end of said capacitor;

(c) a second diode having a second anode and a second cathode, said second anode being coupled to said second end of said capacitor and said second cathode being coupled to a higher voltage than the common voltage,

the zero current detector producing an output voltage at said second end of said capacitor indicative of the inductor current.

10. The zero current detector as in claim 9, wherein the inductor has an inductor current ranging over negative, zero, and positive values, the zero current detector being adapted so that said output voltage has a first level when the inductor current ranges over a positive value, and so that said output voltage has a second level when the inductor current ranges over a negative value.

11. The zero current detector of claim 10, wherein said first voltage level is substantially equal to said higher voltage, and said second voltage level is substantially equal to the common voltage.

12. The zero current detector of claim 10, wherein said output voltage is adapted to transition from said first level to said second level when the inductor current decreases from a positive value and substantially reaches a zero value.

13. The zero current detector of claim 10, wherein said output voltage is adapted to transition from said second level to said first level when the inductor current increases from a negative value and substantially reaches a zero value.

14. A power converter for providing power factor correction, the power converter comprising:

(a) an inductor having an inductor current, said inductor current ranging over negative, zero, and positive values;

(b) a switching transistor having a parasitic capacitance, the switching transistor being coupled from one end of said inductor to a common voltage;

(c) a zero current detector adapted to output a zero current sense output when said inductor current is substantially zero;

(d) a minimum current discriminator adapted to output a minimum current signal when said inductor current reaches a predetermined value;

(e) a timing circuit adapted to output a timing signal at the end of a predetermined effective time interval after being activated;

(f) a pulse-width modulator for turning on and turning off said switching transistor, said pulse-width modulator receiving said zero current signal, said minimum current signal, and said timing signal, said pulse-width modulator being adapted to;

i) turn on said switching transistor when said zero current sense output is received;

ii) activate said timing circuit when said minimum current signal is received; and

iii) turn off said switching transistor when said timing signal is received.