Phase locked loop using a schmitt trigger block

• US 6,043,695 A
• Filed: 05/28/1998
• Issued: 03/28/2000
• Est. Priority Date: 05/29/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: O'Sullivan, Eugene
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US09/086,225
• Time in Patent Office: 670 Days
• Field of Search: 327/155, 327/156, 327/157, 331/1 A, 331/17, 331/25, 331/111, 331/153
• US Class Current: 327/157
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A phase locked loop (PLL) circuit is described which uses a Schmitt trigger block (28) to achieve a very small steady state phase error at an input of a phase comparator block (21) over the entire PLL lock voltage range. The amount of hysteresis which each Schmitt trigger circuit (281, 282) in the Schmitt trigger block (28) has depends on the damping factor ζ of the PLL circuit as well as the temperature and voltage coefficients of a VCO'"'"'s input voltage. The midpoint of the positive and the negative thresholds of the hysteresis curve of each Schmitt trigger circuit (281, 282) is set by the current voltage characteristics of charge pump circuits in a charge pump block (22). Responsive to the PLL'"'"'s lock voltage (VCNT), the Schmitt trigger block (28) commands a control logic circuit (29) to turn ON or turn OFF as the case may be PMOS pump UP transistors to that of NMOS pump DOWN transistors. It is this ratio which determines the PLL'"'"'s steady state phase error. In one embodiment, a frequency divider (25) is used between the VCO (24) and the phase comparator block (21). In another embodiment, this divider (25) is removed and the output of the VCO is fed directly back to the phase comparator block.

Claims

1. A phase locked loop (PLL) circuit using a Schmitt trigger to achieve a very small steady state phase error, said PLL circuit comprising:

a phase comparator block for detecting a phase difference between an input reference signal and a feedback signal to produce a phase difference signal indicative of the phase difference;

a low-pass filter block for producing a control voltage;

a charge pump block, placed between said phase comparator block and said low-pass filter block, for charging or discharging said low-pass filer block according to the phase difference signal;

a Schmitt trigger block, connected to said low-pass filter block, consisting of a plurality of Schmitt trigger circuits, each Schmitt trigger circuit having the amount of hysteresis which depends on a damping factor ζ

of the PLL circuit as well as temperature and voltage coefficients of the control voltage, a hysteresis curve having the midpoint which is set by a current voltage characteristics of said charge pump block, said Schmitt trigger block producing Schmitt output signals which vary in response to the control voltage;

a control logic circuit placed between said Schmitt trigger block and said charge pump block, said control logic circuit producing control output signals which vary in response to the Schmitt output signals, the control output signals commanding said charge pump block to turn ON or OFF;

a voltage controlled oscillator (VCO), connected to said low-pass filter block, for generating a VCO output signal whose frequency is determined by the control voltage; and

a frequency divider, placed between said voltage controlled oscillator and said phase comparator block, for frequency dividing the VCO output signal by a division ratio N, said frequency divider producing a divided signal as the feedback signal which is supplied to said phase comparator block.

2. A PLL circuit as claimed in claim 1, wherein said voltage controlled oscillator consists of a bias generator (BG) and a current controlled oscillator (CCO).

3. A PLL circuit as claimed in claim 1, wherein

said phase comparator block consists of a single phase comparator, said single phase comparator having a first input terminal, a second input terminal, a first output terminal, and a second output terminal;

said charge pump block consisting of a first charge pump circuit and a second charge pump circuit,

said first charge pump circuit consisting of

a first PMOS pump UP transistor which charges said low-pass filter block when its gate voltage goes from a logic high level to a logic low level, whose source is connected to a VDD power supply and whose drain is connected to an input terminal of said low-pass filter block,

a first NMOS pump DOWN transistor which discharges said low-pass filter block when its gate voltage goes from a logic low level to a logic high level, whose source is connected to GND and whose drain is connected to the input terminal of said low-pass filter block,

buffer inverters for buffering a signal from the first output terminal of said phase comparator to the gate of said first PMOS pump UP transistor,

inverter(s) for inverting a signal from the second output terminal of said phase comparator to drive the gate of said first NMOS pump DOWN transistor,

said second charge pump circuit consisting of

a second PMOS pump UP transistor which charges said low-pass filter block when its gate voltage goes from a logic high level to a logic low level, whose source is connected to the VDD power supply and whose drain is connected to the input terminal of said low-pass filter block,

a second NMOS pump DOWN transistor which discharges said low-pass filter block when its gate voltage goes from a logic low level to a logic high level, whose source is connected to GND and whose drain is connected to the input terminal of said low-pass filter block,

said Schmitt trigger block consisting of a first Schmitt trigger circuit and a second Schmitt trigger circuit,

said first Schmitt trigger circuit having a first positive threshold at Vref1+ and a first negative threshold at Vref1-, a first threshold difference (Vref1+-Vref1-) depending on the damping factor ζ

of the PLL circuit as well as the temperature and voltage characteristics of the control voltage, a first threshold Vref1=(Vref1++Vref1)-)/2 being determined by current-voltage characteristics of the transistors in said first charge pump circuit, the first threshold Vref1 closer to GND than it is to VDD,

said second Schmitt trigger circuit having a second positive threshold at Vref2+ and a second negative threshold at Vref2-, a second threshold difference (Vref2+-Vref2-) depending on the damping factor ζ

of the PLL circuit as well as the temperature and voltage characteristics of the control voltage, a second threshold Vref2=(Vref2++vref2-)/2 being determined by current-voltage characteristics of the transistors in said first charge pump circuit, the second threshold Vref2 closer to VDD than it is to GND.

4. A PLL circuit as claimed in claim 3, wherein said control logic circuit consists of a 2-input NAND gate and a 2-input AND gate, said NAND gate having a first input terminal connected to an output terminal of said second Schmitt trigger circuit and a second input terminal connected to an inverse signal of the first output terminal of said phase comparator, said AND gate having a first input terminal connected to an output terminal of said first Schmitt trigger circuit and a second input terminal connected to the inverse signal of the second output terminal of said phase comparator, said NAND gate having an output terminal connected to the gate of said second PMOS pump UP transistor in said second charge pump circuit, said AND gate having an output terminal connected to the gate of said second NMOS pump DOWN transistor in said second charge pump circuit.

5. A PLL circuit as claimed in claim 4, which further comprises current sources between the sources of the pump transistors (NMOS and PMOS) and their respective power-supplies (GND and VDD respectively).

6. A PLL circuit as claimed in claim 3, wherein

said charge pump block further comprises a switch bank and full-swing buffer inverters,

said switch bank comprising a plurality of switches whose gates are controlled by the control output signals of said control logic circuit, said switches controlling which of the PMOS pump UP transistors and the NMOS pump DOWN transistors are ON at any one time,

said full-swing buffer inverters being placed between the switches and the gates of both PMOS pump UP transistors and NMOS pump DOWN transistors to guarantee that these transistors experience a full VDD logic swing,

said control logic circuit having a first input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, said control logic circuit consisting of a first inverter and a second inverter, said first inverter having an input terminal which is connected to the output terminal of said first Schmitt trigger circuit and to the first output terminal of said control logic circuit, said second inverter having an input terminal which is connected to the output terminal of said second Schmitt trigger circuit and to the third output terminal of said control logic circuit, said first inverter having an output terminal connected to the second output terminal of said control logic circuit, said second inverter having an output terminal connected to the fourth output terminal of said control logic circuit.

7. A PLL circuit as claimed in claim 6, which further comprises current sources between the sources of the pump transistors (NMOS and PMOS) and their respective power-supplies (GND and VDD respectively).

8. A phase locked loop (PLL) circuit using a Schmitt trigger to achieve a very small steady state phase error, said PLL circuit comprising:

a phase comparator block for detecting a phase difference between an input reference signal and a feedback signal to produce a phase difference signal indicative of the phase difference;

a low-pass filter block for producing a control voltage;

a charge pump block, placed between said phase comparator block and said low-pass filter block, for charging or discharging said low-pass filer block according to the phase difference signal;

a Schmitt trigger block, connected to said low-pass filter block, consisting of a plurality of Schmitt trigger circuits, each Schmitt trigger circuit having the amount of hysteresis which depends on a damping factor ζ

of the PLL circuit as well as temperature and voltage coefficients of the control voltage, a hysteresis curve having the midpoint which is set by a current voltage characteristics of said charge pump block, said Schmitt trigger block producing Schmitt output signals which vary in response to the control voltage;

a control logic circuit placed between said Schmitt trigger block and said charge pump block, said control logic circuit producing control output signals which vary in response to the Schmitt output signals, the control output signals commanding said charge pump block to turn ON or OFF;

a voltage controlled oscillator (VCO), connected to said low-pass filter block, for generating a VCO output signal whose frequency is determined by the control voltage; and

supplying means, placed between said voltage controlled oscillator and said phase comparator block, for directly supplying, as the feedback signal, the VCO output signal to said phase comparator block.

9. A PLL circuit as claimed in claim 8, wherein said voltage controlled oscillator consists of a bias generator (BG) and a current controlled oscillator (CCO).

10. A PLL circuit as claimed in claim 8, wherein

said phase comparator block consists of a single phase comparator, said single phase comparator having a first input terminal, a second input terminal, a first output terminal, and a second output terminal;

said charge pump block consisting of a first charge pump circuit and a second charge pump circuit,

said first charge pump circuit consisting of

a first PMOS pump UP transistor which charges said low-pass filter block when its gate voltage goes from a logic high level to a logic low level, whose source is connected to a VDD power supply and whose drain is connected to an input terminal of said low-pass filter block,

a first NMOS pump DOWN transistor which discharges said low-pass filter block when its gate voltage goes from a logic low level to a logic high level, whose source is connected to GND and whose drain is connected to the input terminal of said low-pass filter block,

buffer inverters for buffering a signal from the first output terminal of said phase comparator to the gate of said first PMOS pump UP transistor,

inverter (s) for inverting a signal from the second output terminal of said phase comparator to drive the gate of said first NMOS pump DOWN transistor,

said second charge pump circuit consisting of

a second PMOS pump UP transistor which charges said low-pass filter block when its gate voltage goes from a logic high level to a logic low level, whose source is connected to the VDD power supply and whose drain is connected to the input terminal of said low-pass filter block,

a second NMOS pump DOWN transistor which discharges said low-pass filter block when its gate voltage goes from a logic low level to a logic high level, whose source is connected to GND and whose drain is connected to the input terminal of said low-pass filter block,

said Schmitt trigger block consisting of a first Schmitt trigger circuit and a second Schmitt trigger circuit,

said first Schmitt trigger circuit having a first positive threshold at Vref1+ and a first negative threshold at Vref1-, a first threshold difference (Vref1+-Vref1-) depending on the damping factor ζ

of the PLL circuit as well as the temperature and voltage characteristics of the control voltage, a first threshold Vref1=(Vref1++Vref1-)/2 being determined by current-voltage characteristics of the transistors in said first charge pump circuit, the first threshold vref1 closer to GND than it is to VDD,

said second Schmitt trigger circuit having a second positive threshold at Vref2+ and a second negative threshold at Vref2-, a second threshold difference (Vref2+-Vref2-) depending on the damping factor ζ

of the PLL circuit as well as the temperature and voltage characteristics of the control voltage, a second threshold Vref2=(Vref2++Vref2-)/2 being determined by current-voltage characteristics of the transistors in said first charge pump circuit, the second threshold Vref2 closer to VDD than it is to GND.

11. A PLL circuit as claimed in claim 10, wherein said control logic circuit consists of a 2-input NAND gate and a 2-input AND gate, said NAND gate having a first input terminal connected to an output terminal of said second Schmitt trigger circuit and a second input terminal connected to an inverse signal of the first output terminal of said phase comparator, said AND gate having a first input terminal connected to an output terminal of said first Schmitt trigger circuit and a second input terminal connected to the inverse signal of the second output terminal of said phase comparator, said NAND gate having an output terminal connected to the gate of said second PMOS pump UP transistor in said second charge pump circuit, said AND gate having an output terminal connected to the gate of said second NMOS pump DOWN transistor in said second charge pump circuit.

12. A PLL circuit as claimed in claim 11, which further comprises current sources between the sources of the pump transistors (NMOS and PMOS) and their respective power-supplies (GND and VDD respectively).

13. A PLL circuit as claimed in claim 10, wherein

said charge pump block further comprises a switch bank and full-swing buffer inverters,

said switch bank comprising a plurality of switches whose gates are controlled by the control output signals of said control logic circuit, said switches controlling which of the PMOS pump UP transistors and the NMOS pump DOWN transistors are ON at any one time,

said full-swing buffer inverters being placed between the switches and the gates of both PMOS pump UP transistors and NMOS pump DOWN transistors to guarantee that these transistors experience a full VDD logic swing,

said control logic circuit having a first input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, said control logic circuit consisting of a first inverter and a second inverter, said first inverter having an input terminal which is connected to the output terminal of said first Schmitt trigger circuit and to the first output terminal of said control logic circuit, said second inverter having an input terminal which is connected to the output terminal of said second Schmitt trigger circuit and to the third output terminal of said control logic circuit, said first inverter having an output terminal connected to the second output terminal of said control logic circuit, said second inverter having an output terminal connected to the fourth output terminal of said control logic circuit.

14. A PLL circuit as claimed in claim 13, which further comprises current sources between the sources of the pump transistors (NMOS and PMOS) and their respective power-supplies (GND and VDD respectively).