Level shift circuit

• US 6,043,699 A
• Filed: 11/03/1998
• Issued: 03/28/2000
• Est. Priority Date: 11/04/1997
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Advanced Technologies Inc. (f/k/a Tessera Advanced Technologies, Inc.) (Adeia Inc.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Shimizu, Yasuhide
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US09/184,975
• Time in Patent Office: 511 Days
• Field of Search: 327/333, 327/374, 327/382, 327/427, 327/437, 327/391, 327/108, 327/198, 327/55, 327/228, 326/21, 326/22, 326/23, 326/63, 326/64, 326/80, 326/81
• US Class Current: 327/333
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A level shift circuit reduced in a circuit area and conversion delay when converting a signal level, capable of operating at a high speed, expanded in the range of the operatable voltage, and capable of operating at a low voltage, including a first transistor connected between a voltage Va source and an output terminal, a second transistor connected between a voltage Vc source and an output terminal, a third transistor connected between a voltage Vc source and a gate of the second transistor, a fourth transistor connected between a voltage Va source and the gate of the second transistor, a fifth transistor connected between the ground and the output terminal, and a sixth transistor connected between the ground and the gate of the second transistor, wherein a connection point of an output terminal and the first, second, and fifth transistors is connected to a gate of the third transistor, gates of the fourth and fifth transistors are connected to an input terminal, and an inverted signal of an input signal to the input terminal is supplied to gates of the first and sixth transistors.

Claims

1. A level shift circuit, comprising:

an input terminal connected to an input side circuit operating by a first power source voltage and a second power source voltage;

an output terminal connected to an output side circuit operating by a third power source voltage and a fourth power source voltage which are different from the voltage of the input side circuit;

a first node;

a second node;

a first transistor of a first conductivity type channel connected between a voltage source of the first power source voltage and the first node;

a second transistor of a second conductivity type channel connected between a voltage source of the third power source voltage and the first node;

a third transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the second node;

a fourth transistor of the first conductivity type channel connected between the voltage source of the first power source voltage and the second node;

a fifth transistor of the first conductivity type channel connected between one of the voltage sources of the second power source voltage and the fourth power source voltage and the first node; and

a sixth transistor of the first conductivity type channel connected between one of the voltage sources of the second power source voltage and the fourth power source voltage and the second node; and

wherein

the first node is connected to a gate of the third transistor, the second node is connected to a gate of the second transistor, and gates of the fourth and fifth transistors are connected to the input terminal;

an inverted signal of an input signal input to the input terminal is supplied to gates of the first and sixth transistors; and

one of the first node and the second node is connected to the output terminal.

2. A level shift circuit as set forth in claim 1, wherein the first conductivity type channel is an n-channel, and the second conductivity type channel is a p-channel.

3. A level shift circuit as set forth in claim 1, wherein the first conductivity type channel is a p-channel, and the second conductivity type channel is an n-channel.

4. A level shift circuit as set forth in claim 1, wherein the third power source voltage is higher than the first power source voltage, and the second and fourth voltages are a ground voltage.

5. A level shift circuit as set forth in claim 2, wherein the third power source voltage is higher than the first power source voltage, and the second and fourth voltages are a ground voltage.

6. A level shift circuit as set forth in claim 1, wherein one of the terminals of each the fifth and sixth transistors is connected to the voltage source of the fourth power source voltage, and the third power source voltage is higher than the first power source voltage.

7. A level shift circuit as set forth in claim 2, wherein one of the terminals of the fifth and sixth transistors is connected to the voltage source of the fourth power source voltage, and the third power source voltage is higher than the first power source voltage.

8. A level shift circuit, comprising:

an input terminal connected to an input side circuit operating by a first power source voltage and a second power source voltage;

an output terminal connected to an output side circuit operating by a third power source voltage and a fourth power source voltage which are different from the voltage of the input side circuit;

a first node;

a second node;

a first transistor of a first conductivity type channel connected between a voltage source of the fourth power source voltage and the first node;

a second transistor of a second conductivity type channel connected between a voltage source of the second power source voltage and the first node;

a third transistor of the first conductivity type channel connected between the voltage source of the fourth power source voltage and the second node;

a fourth transistor of the second conductivity type channel connected between the voltage source of the second power source voltage and the second node;

a fifth transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the first node; and

a sixth transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the second node; and

wherein

the first node is connected to a gate of the third transistor, the second node is connected to a gate of the first transistor, and gates of the fourth and fifth transistors are connected to the input terminal;

an inverted signal of an input signal input to the input terminal is supplied to gates of the second and sixth transistors; and

one of the first node and the second node is connected to the output terminal.

9. A level shift circuit as set forth in claim 8, wherein the first conductivity type channel is an n-channel, and the second conductivity type channel is a p-channel.

10. A level shift circuit as set forth in claim 8, wherein the first conductivity type channel is a p-channel, and the second conductivity type channel is an n-channel.

11. A level shift circuit as set forth in claim 8, wherein the fourth power source voltage is less than the second power source voltage.

12. A level shift circuit as set forth in claim 9, wherein the fourth power source voltage is less than the second power source voltage.

13. A level shift circuit, comprising:

a circuit input terminal connected to an input side circuit operating by a first power source voltage and a second power source voltage;

a circuit output terminal connected to an output side circuit operating by a third power source voltage and a fourth power source voltage which are different from the voltage of the input side circuit;

a plurality of level shift stages, each having a non-inverted output terminal, an inverted output terminal, a first transistor of a first conductivity type channel connected between a voltage source of the first power source voltage and the non-inverted output terminal, a second transistor of a second conductivity type channel connected between a voltage source of the third power source voltage and the non-inverted output terminal, a third transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the inverted output terminal, a fourth transistor of the first conductivity type channel connected between the voltage source of the first power source voltage and the inverted output terminal, a fifth transistor of the first conductivity type channel connected between one of the voltage sources of the second power source voltage and the fourth power source voltage and the non-inverted output terminal, and a sixth transistor of the first conductivity type channel connected between one of the voltage sources of the second power source voltage and the fourth power source voltage and the inverted output terminal, and wherein a common connection point of the non-inverted output terminal;

the first, second, and fifth transistors is connected to a gate of the third transistor and a common connection point of the inverted output terminal;

the third, fourth, and sixth transistors is connected to a gate of the second transistor; and

wherein

the non-inverted output terminal of a previous stage is connected to gates of the fourth and fifth transistors of a later stage, the inverted output terminal of the previous stage is connected to gates of the first and sixth transistors of the later stage;

gates of the fourth and fifth transistors of a initial stage is connected to the circuit input terminal;

an inverted signal of an input signal input to the circuit input terminal is supplied to gates of the first and sixth transistors; and

one of the non-inverted output terminal and the inverted output terminal is connected to the circuit output terminal.

14. A level shift circuit as set forth in claim 13, wherein the first conductivity type channel is an n-channel, and the second conductivity type channel is a p-channel.

15. A level shift circuit as set forth in claim 13, wherein the third power source voltage is higher than the first power source voltage.

16. A level shift circuit as set forth in claim 13, wherein one each of the terminals of the fifth and sixth transistors is respectively connected to the voltage source of the fourth power source voltage, and the third power source voltage is higher than the first power source voltage.

17. A level shift circuit, comprising:

a circuit input terminal connected to an input side circuit operating by a first power source voltage and a second power source voltage;

a circuit output terminal connected to an output side circuit operating by a third power source voltage and a fourth power source voltage which are different from the voltage of the input side circuit;

a plurality of level shift stages, each having a non-inverted output terminal, an inverted output terminal, a first transistor of a first conductivity type channel connected between a voltage source of the fourth power source voltage and the non-inverted output terminal, a second transistor of a second conductivity type channel connected between a voltage source of the second power source voltage and the non-inverted output terminal, a third transistor of the first conductivity type channel connected between the voltage source of the fourth power source voltage and the inverted output terminal, a fourth transistor of the second conductivity type channel connected between the voltage source of the second power source voltage and the inverted output terminal, a fifth transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the non-inverted output terminal, and a sixth transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the inverted output terminal, and wherein a common connection point of the non-inverted output terminal and the first, second, and fifth transistors is connected to a gate of the third transistor and a common connection point of the inverted output terminal, and the third, fourth, and sixth transistors is connected to a gate of the first transistor; and

wherein

the non-inverted output terminal of a previous stage is connected to gates of the fourth and fifth transistors of a later stage, and the inverted output terminal of the previous stage is connected to gates of the second and sixth transistors of the later stage;

gates of the fourth and fifth transistors of an initial stage are connected to the circuit input terminal;

an inverted signal of an input signal input to the circuit input terminal is supplied to gates of the second and sixth transistors; and

one of the non-inverted output terminal and the inverted output terminal is connected to the circuit output terminal.

18. A level shift circuit as set forth in claim 17, wherein the first conductivity type channel is an n-channel, and the second conductivity type channel is a p-channel.

19. A level shift circuit as set forth in claim 17, wherein the fourth power source voltage is less than the second power source voltage.

20. A level shift circuit, comprising:

a circuit input terminal connected to an input side circuit operating by a first power source voltage and a second power source voltage;

a circuit output terminal connected to an output side circuit operating by a third power source voltage and a fourth power source voltage which are different from the voltage of the input side circuit;

a first level shift stage having a first non-inverted output terminal, a first inverted output terminal, a first transistor of a first conductivity type channel connected between a voltage source of the first power source voltage and the first non-inverted output terminal, a second transistor of a second conductivity type channel connected between a voltage source of the third power source voltage and the first non-inverted output terminal, a third transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the first inverted output terminal, a fourth transistor of the first conductivity type channel connected between the voltage source of the first power source voltage and the first inverted output terminal, a fifth transistor of the first conductivity type channel connected between one of the voltage sources of the second power source voltage and the fourth power source voltage and the first non-inverted output terminal, and a sixth transistor of the first conductivity type channel connected between one of the voltage sources of the second power source voltage and the fourth power source voltage and the first inverted output terminal, and wherein a common connection point of the first non-inverted output terminal and the first, second, and fifth transistors is connected to a gate of the third transistor and a common connection point of the second inverted output terminal and the third, fourth, and sixth transistors is connected to a gate of the second transistor; and

a second level shift stage having a second non-inverted output terminal, a second inverted output terminal, a seventh transistor of a first conductivity type channel connected between a voltage source of the fourth power source voltage and the second non-inverted output terminal, an eighth transistor of a second conductivity type channel connected between a voltage source of the second power source voltage and the second non-inverted output terminal, a ninth transistor of the first conductivity type channel connected between the voltage source of the fourth power source voltage and the second inverted output terminal, a 10th transistor of the second conductivity type channel connected between the voltage source of the second power source voltage and the second inverted output terminal, an 11th transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the second non-inverted output terminal, and a 12th transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the second inverted output terminal, and wherein a common connection point of the second non-inverted output terminal and the seventh, eighth, and 11th transistors is connected to a gate of the ninth transistor and a common connection point of the second inverted output terminal and the ninth, 10th, and 11th transistors is connected to a gate of the seventh transistor; and

wherein

the first non-inverted output terminal of the first level shift stage is connected to gates of the 10th and 11th transistors of the second level shift stage, the first inverted output terminal of the first level shift stage is connected to gates of the eighth and 12th transistors of the second level shift stage;

gates of the fourth and fifth transistors of a the first level shift stage is connected to the circuit input terminal;

an inverted signal of an input signal input to the circuit input terminal is supplied to gates of the first and sixth transistors; and

one of the second non-inverted output terminal and the second inverted output terminal of the second level shift stage is connected to the circuit output terminal.

21. A level shift circuit as set forth in claim 20, wherein the first conductivity type channel is an n-channel, and the second conductivity type channel is a p-channel.

22. A level shift circuit, comprising:

a circuit input terminal connected to an input side circuit operating by a first power source voltage and a second power source voltage;

a circuit output terminal connected to an output side circuit operating by a third power source voltage and a fourth power source voltage which are different from the voltage of the input side circuit;

a first level shift stage having a first non-inverted output terminal, a first inverted output terminal, a first transistor of a first conductivity type channel connected between a voltage source of the fourth power source voltage and the first non-inverted output terminal, a second transistor of a second conductivity type channel connected between a voltage source of the second power source voltage and the first non-inverted output terminal, a third transistor of the first conductivity type channel connected between the voltage source of the fourth power source voltage and the first inverted output terminal, a fourth transistor of the second conductivity type channel connected between the voltage source of the second power source voltage and the first inverted output terminal, a fifth transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the first non-inverted output terminal, and a sixth transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the first inverted output terminal, and wherein a common connection point of the first non-inverted output terminal and the first, second, and fifth transistors is connected to a gate of the third transistor and a common connection point of the first inverted output terminal, the third, fourth, and sixth transistors is connected to a gate of the first transistor; and

a second level shift stage having a second non-inverted output terminal, a second inverted output terminal, a seventh transistor of a first conductivity type channel connected between a voltage source of the first power source voltage and the second non-inverted output terminal, an eighth transistor of a second conductivity type channel connected between a voltage source of the third power source voltage and the second non-inverted output terminal, a ninth transistor of the second conductivity type channel connected between the voltage source of the third power source voltage and the second inverted output terminal, a 10th transistor of the first conductivity type channel connected between the voltage source of the first power source voltage and the second inverted output terminal, an 11th transistor of the first conductivity type channel connected between one of the voltage sources of the second power source voltage and the fourth power source voltage and the second non-inverted output terminal, and a 12th transistor of the first conductivity type channel connected between the voltage sources of the second power source voltage and the fourth power source voltage and the second inverted output terminal, and wherein a common connection point of the second non-inverted output terminal and the seventh, eighth, and 11th transistors is connected to a gate of the ninth transistor and a common connection point of the second inverted output terminal, the ninth, 10th, and 12th transistors is connected to a gate of the eighth transistor; and

wherein

the first non-inverted output terminal of the first level shift stage is connected to gates of the 10th and 11th transistors of the second level shift stage, and the first inverted output terminal of the first level shift stage is connected to gates of the seventh and 12th transistors of the second level shift stage;

gates of the fourth and fifth transistors of a the first level shift stage are connected to the circuit input terminal;

an inverted signal of an input signal input to the circuit input terminal is supplied to gates of the first and sixth transistors; and

one of the second non-inverted output terminal and the second inverted output terminal of the second level shift stage is connected to the circuit output terminal.

23. A level shift circuit as set forth in claim 22, wherein the first conductivity type channel is an n-channel, and the second conductivity type channel is a p-channel.