Frequency detection circuit

• US 6,043,749 A
• Filed: 04/16/1998
• Issued: 03/28/2000
• Est. Priority Date: 04/16/1997
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Saito, Hirofumi, Funahashi, Norio
• Primary Examiner(s): Hofsass, Jeffery A.
• Assistant Examiner(s): TRIEU, VAN THANH
• Application Number:
  US09/060,818
• Time in Patent Office: 712 Days
• Field of Search: 340/657, 340/658, 340/656, 340/660, 340/661, 340/870.26, 340/521, 714/814, 324/76.66, 324/76.39, 331/26, 331/27, 331/49
• US Class Current: 340/658
• CPC Class Codes: G01R 23/09 using analogue integrators, e.g. capacitors establishing a mean value by balance of input signals and defined discharge signals or leakage

Abstract

A frequency detection circuit has a transistor switching device between first and second electric potentials, and a gate applied with a clock signal. A resistor and a capacitor are connected in parallel between the output of the transistor switching device and the second potential. The capacitor is charged toward the first potential when the clock signal assumes one level and discharged toward the second potential in accordance with a time constant determined by the resistor and the capacitor when the clock signal changes to the other level. A comparison device connected to the output of the transistor switching device compares an output voltage of the transistor switching device with a predetermined threshold voltage and delivers an AC signal when the clock signal is small causing the output voltage of the transistor switching device to cross the threshold voltage during discharge of the capacitor, but a DC signal when the frequency of the clock signal is large causing the output voltage of the transistor switching device not to cross the threshold voltage.

Claims

1. A frequency detection circuit comprising:

a transistor switch, connected between a first electric potential and a second electric potential, having a gate applied with a clock signal to be measured;

a resistor and a capacitor, which both are connected in parallel between the output of said transistor switch and said second electric potential, said capacitor being charged toward said first electric potential through an on-resistance of said transistor switch when the measured clock signal assumes one level and discharged toward said second electric potential through said resistor in accordance with a time constant determined by a resistance of said resistor and a capacitance of said capacitor when the measured clock signal changes to the other level; and

a comparator, connected to the output of said transistor switch, for comparing an output voltage of said transistor switch with a predetermined threshold voltage supplied to said comparator and delivering a signal of alternating waveform when the frequency of the measured clock signal is smaller as compared to said time constant and the output voltage of said transistor switch crosses said threshold voltage during discharge of said capacitor, and said comparator delivering a signal of constant level when the frequency of the measured clock signal is larger as compared to said time constant and the output of said transistor switch does not cross said threshold voltage.

3. A frequency detection circuit according to claim 1, wherein said frequency detection circuit is applied to one of a central processing unit (CPU) or an electrically erasable programmable read-only memory (EEPROM) to detect a frequency for use in said CPU or said EEPROM, and components of said frequency detection circuit and said CPU or said EEPROM are formed on a single semiconductor substrate.

2. A frequency detection circuit comprising:

a first stage including a first transistor switch, connected between a first electric potential and a second electric potential, having a gate applied with a clock signal to be measured, a first resistor and a first capacitor, which are both connected in parallel between the output of said first transistor switch and said second electric potential, and a first comparator connected to the output of said first transistor switch and supplied with a first threshold voltage, said first capacitor being charged toward said first electric potential through an on-resistance of said first transistor switch when the measured clock signal assumes one level and discharged toward said second electric potential through said first resistor in accordance with a first time constant determined by a resistance of said first resistor and a capacitance of said first capacitor;

a second stage connected in series with said first stage and including a second transistor switch, connected between said first electric potential and said second electric potential, having a gate connected to the output of said first comparator, a second resistor and a second capacitor connected in parallel between the output of said second transistor switch and said second electric potential, and a second comparator connected to the output of said second transistor switch and supplied with a second threshold voltage which is different from said first threshold voltage, said second capacitor being charged toward said first electric potential through an on-resistance of said second transistor switch when the measured clock signal assumes the other level and discharged toward said second electric potential through said second resistor in accordance with a second time constant which is different from said first time constant and determined by a resistance of said second resistor and a capacitance of said second capacitor; and

a latch circuit connected to receive an output signal of said second stage, said latch circuit being cooperative with said first and second stages to deliver a signal of one level when the frequency of the measured clock signal is a prescribed frequency, a signal having the other level and indicative of an upper limit of said prescribed frequency when the frequency of the measured clock signal changes from the prescribed frequency to a first frequency which is larger as compared to said first time constant of said first stage, and a signal having the aforementioned other level and indicative of a lower limit of said prescribed frequency when the frequency of the measured clock signal changes from said prescribed frequency to a second frequency which is smaller as compared to said second time constant of said second stage.

4. A frequency detection circuit according to claim 2, wherein said frequency detection circuit is applied to one of a central processing unit (CPU) or an electrically erasable programmable read-only memory (EEPROM) to detect a frequency for use in said CPU or said EEPROM, and components of said frequency detection circuit and said CPU or said EEPROM are formed on a single semiconductor substrate.