Asymmetry correction for a read head

• US 6,043,943 A
• Filed: 04/30/1997
• Issued: 03/28/2000
• Est. Priority Date: 12/31/1996
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Rezzi, Francesco, Patti, Giuseppe
• Primary Examiner(s): Faber, Alan
• Application Number:
  US08/846,782
• Time in Patent Office: 1,063 Days
• Field of Search: 360/67, 360/65, 360/46, 327/553, 330/254, 330/278, 330/282
• US Class Current: 360/46
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 2005/0016 of magnetoresistive transducers
• CPC Class Codes: G11B 5/012 Recording on, or reproducing or erasing from, magnetic disks G11B17/00, G11B19/00 take precedence
• CPC Class Codes: G11B 5/09 Digital recording

Abstract

A method and a circuit for correcting asymmetry in a response signal generated by a magneto-resistive head. The magneto-resistive head generates a response signal to transmit digital information read from a magnetic media storage device. The asymmetry is corrected in a negative feedback manner by squaring an output signal, modulating the squared output signal, and subtracting the modulated squared output signal from the response signal to generate the output signal. The circuit employs a differential amplifier as an input stage and a Gilbert multiplier circuit to square the output signal.

Claims

1. An asymmetry correction circuit for generating an output signal from an asymmetric input signal, the asymmetric input signal being produced by a magneto-resistive head, the circuit comprising:

an input stage receiving an asymmetric input signal and generating an output signal at an output, the input stage having a subtraction terminal; and

a squaring circuit having a modulation stage, the squaring circuit having an input connected to the output of the input stage to receive the output signal and having an output connected to the modulation stage and to the subtraction terminal of the input stage to provide a modulated squared output signal to the subtraction terminal for subtraction from the asymmetric input signal.

2. The asymmetry correction circuit of claim 1 wherein the input stage comprises a differential amplifier having a differential input, a differential output, and a subtraction terminal.

3. The asymmetry correction circuit of claim 1 wherein the squaring circuit comprises a Gilbert multiplier circuit having two differential input ports, a differential output port, and a modulation stage, both of the differential input ports receiving the output signal, the differential output port being coupled to the subtraction terminal of the input stage, the Gilbert multiplier circuit generating the modulated squared output signal at the differential output port.

4. The asymmetry correction circuit of claim 1 wherein the modulation stage comprises an adjustable modulating impedance.

5. The asymmetry correction circuit of claim 4 wherein the adjustable modulating impedance comprises at least one trimmed resistor.

6. The asymmetry correction circuit of claim 4 wherein the adjustable modulating impedance comprises a programmable resistor having a resistance value, the resistance value being selected by a digital-to-analog converter in response to a calibration value stored in a register.

7. The asymmetry correction circuit of claim 1 wherein the squaring circuit comprises a Gilbert multiplier circuit having first and second differential input ports, a differential output port, and a modulation stage, the first differential input port receiving the output signal, the second differential input port receiving an attenuated output signal, the differential output port being coupled to the subtraction terminal of the input stage, the Gilbert multiplier circuit generating the modulated squared output signal at the differential output port.

8. The asymmetry correction circuit of claim 7 wherein the modulation stage is comprised of at least one controlled current source.

9. The asymmetry correction circuit of claim 8 wherein the modulation stage is comprised of a plurality of controlled current sources each generating a current, the current generated by each controlled current source being controlled by a digital-to-analog converter based on a calibration value stored in a register.

10. An asymmetry correction circuit for generating an output signal from an asymmetric input signal produced by a magneto-resistive head, comprising:

a multiplier circuit having a plurality of input terminals, an output terminal, and a modulation element; and

an amplifier having an input and an output, the output of the amplifier being connected to the input terminals of the multiplier circuit to square the output signal by multiplying the output signal by itself, the output of the amplifier being connected to a circuit output port, the amplifier further having a subtraction terminal connected to the output terminal of the multiplier circuit to receive a modulated squared output signal from the modulation element.

11. The asymmetry correction circuit of claim 10 wherein the multiplier circuit comprises a Gilbert multiplier circuit.

12. The asymmetry correction circuit of claim 10 wherein the modulation element comprises an adjustable modulating impedance.

13. The asymmetry correction circuit of claim 12 wherein the adjustable modulating impedance comprises an adjustable resistance.

14. The asymmetry correction circuit of claim 13 wherein the adjustable resistance comprises at least one trimmed resistor.

15. The asymmetry correction circuit of claim 12 wherein the adjustable modulating impedance comprises a programmable resistor having a resistance value, the resistance value being selected by a digital-to-analog converter in response to a calibration value stored in a register.

16. The asymmetry correction circuit of claim 10 wherein the multiplier circuit comprises a differential multiplier circuit having two differential input terminals and one differential output terminal.

17. The asymmetry correction circuit of claim 16 wherein the amplifier comprises a differential amplifier having a differential input and a differential output, the differential output of the differential amplifier being connected to both differential input terminals of the differential multiplier circuit.

18. The asymmetry correction circuit of claim 10 wherein the modulation element is comprised of at least one controlled current source.

19. The asymmetry correction circuit of claim 18 wherein the modulation element is comprised of a plurality of controlled current sources each generating a current, the current generated by each controlled current source being controlled by a digital-to-analog converter based on a calibration value stored in a register.

20. The asymmetry correction circuit of claim 10, further comprising a voltage divider circuit interposed between the output of the amplifier and one of the input terminals of the multiplier circuit.

21. The asymmetry correction circuit of claim 10 wherein the input of the amplifier receives the asymmetric input signal and the amplifier generates an output signal at the output of the amplifier, the output signal being applied to the input terminals of the multiplier circuit, the multiplier circuit generating the modulated squared output signal at the output terminal of the multiplier circuit, the modulated squared output signal being applied to the subtraction terminal of the amplifier.

22. A system for reading data from a storage media and generating an information signal, comprising:

a read head reading data from the storage media and generating a first signal in response to the data;

a pre-amplifier receiving the first signal and amplifying the first signal to generate a second signal;

a voltage controlled amplifier receiving the second signal and amplifying the second signal to generate a third signal;

a register storing a calibration value;

a digital-to-analog converter connected to the register to receive the calibration value, the digital-to-analog converter generating a calibration signal based on the calibration value;

an asymmetry correction circuit receiving the third signal and the calibration signal and correcting an asymmetry in the third signal according to the calibration signal to generate a fourth signal;

a filter receiving the fourth signal and filtering the fourth signal to generate a fifth signal; and

a digital signal processing circuit receiving the fifth signal and processing the fifth signal into the information signal.

23. The system of claim 22 wherein the asymmetry correction circuit comprises:

an input stage receiving the third signal and generating the fourth signal at an output, the input stage having a subtraction terminal; and

a squaring circuit having a modulation stage and receiving the calibration signal, the squaring circuit having an input connected to the output of the input stage for receiving the fourth signal and having an output connected to the subtraction terminal of the input stage, the squaring circuit generating a modulated squared fourth signal according to the calibration signal and providing the modulated squared fourth signal to the subtraction terminal for subtraction from the third signal.

24. A method for generating an output signal from an asymmetric input signal produced by a magneto-resistive head, the asymmetric input signal having positive peaks and negative peaks, the method comprising:

squaring the output signal by multiplying the output signal with itself in a multiplier circuit to obtain a squared output signal;

generating a modulated signal by multiplying the squared output signal by a selected ratio in a modulating circuit; and

subtracting the modulated signal from the asymmetric input signal to generate the output signal.

25. The method of claim 24 wherein the multiplier circuit is a Gilbert multiplier circuit.

26. The method of claim 24, further comprising:

calculating a ratio that is a difference between the positive peaks and the negative peaks of the asymmetric input signal normalized by the average value of the positive peaks and the negative peaks; and

dividing the ratio in half to obtain the selected ratio.

27. The method of claim 24, further comprising forcing the asymmetric input signal and the output signal to a ground voltage reference as an initial step.

28. The method of claim 24 wherein subtracting the modulated signal from the asymmetric input signal comprises drawing a current from a subtraction terminal in an amplifier circuit.

29. A method comprising:

providing an asymmetric input signal produced by a magneto-resistive head, the asymmetric input signal having positive and negative peaks;

subtracting a modulated signal from the input signal to generate a first signal;

generating a squared first signal by multiplying the first signal with itself; and

modulating the squared first signal according to a selected ratio to generate the modulated signal.

30. The method of claim 29 wherein modulating the squared first signal comprises multiplying the squared first signal by the selected ratio.

31. The method of claim 29 wherein modulating the squared first signal comprises selecting an impedance value in a Gilbert multiplier circuit.

32. The method of claim 29 wherein modulating the squared first signal comprises regulating one or more variable current sources dynamically with a control logic circuit.

33. The method of claim 29 wherein modulating the squared first signal comprises selecting a current generated by each of a plurality of controlled current generators in a Gilbert multiplier circuit.

34. A method for reading data from a storage media with a plurality of read heads to generate an information signal, comprising:

selecting a first read head;

storing a first calibration value for the first read head in a register;

reading data from the storage media with the first read head and generating a first signal from the first read head in response to the data;

amplifying the first signal to generate a second signal;

subtracting a first modulated signal from the second signal to generate a third signal;

generating a squared third signal by multiplying the third signal with itself;

modulating the squared third signal according to the first calibration value to generate the first modulated signal;

filtering the third signal to generate a fourth signal; and

processing the fourth signal to generate the information signal.

35. The method of claim 34, further comprising:

selecting a second read head;

storing a second calibration value for the second read head in the register;

reading data from the storage media with the second read head and generating a fifth signal from the second read head in response to the data;

amplifying the fifth signal to generate a sixth signal;

subtracting a second modulated signal from the sixth signal to generate a seventh signal;

generating a squared seventh signal by multiplying the seventh signal with itself;

modulating the squared seventh signal according to the second calibration value to generate the second modulated signal;

filtering the seventh signal to generate an eighth signal; and

processing the eighth signal to generate the information signal.

36. A method comprising:

subtracting a modulated signal from an input signal to generate a first signal;

generating a squared first signal by multiplying the first signal with itself; and

modulating the squared first signal by a selected ratio to generate the modulated signal, wherein modulating the squared first signal comprises selecting an impedance value in a Gilbert multiplier circuit.

37. A method comprising:

subtracting a modulated signal from an input signal to generate a first signal;

generating a squared first signal by multiplying the first signal with itself; and

modulating the squared first signal by a selected ratio to generate the modulated signal, wherein modulating the squared first signal comprises regulating one or more variable current sources dynamically with a control logic circuit.

38. A method comprising:

subtracting a modulated signal from an input signal to generate a first signal;

generating a squared first signal by multiplying the first signal with itself; and

modulating the squared first signal by a selected ratio to generate the modulated signal, wherein modulating the squared first signal comprises selecting a current generated by each of a plurality of controlled current generators in a Gilbert multiplier circuit.