Printed circuit board assembly having an integrated fusible link

• US 6,043,966 A
• Filed: 05/13/1999
• Issued: 03/28/2000
• Est. Priority Date: 12/02/1997
• Status: Expired due to Term

• Current Assignee: Littelfuse Incorporated
• Original Assignee: Littelfuse Incorporated
• Inventors: Krueger, David J, Neuhalfen, Andrew J.
• Primary Examiner(s): Jackson, Stephen W.
• Application Number:
  US09/311,016
• Time in Patent Office: 320 Days
• Field of Search: 361/104, 361/103, 361/118, 361/124, 361/38, 337/297
• US Class Current: 361/104
• CPC Class Codes: H01H 69/022 of printed circuit fuses
• CPC Class Codes: H01H 85/046 Fuses formed as printed circuits
• CPC Class Codes: H05K 1/0293 Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
• CPC Class Codes: H05K 2201/0305 Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
• CPC Class Codes: H05K 2201/0338 Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer
• CPC Class Codes: H05K 2201/09727 Varying width along a single conductor; Conductors or pads having different widths
• CPC Class Codes: H05K 2201/10181 Fuse

Abstract

A printed circuit board assembly comprising a printed circuit board having a plurality of conductive traces deposited on a surface thereof to define a plurality of electrical circuit geometries. A plurality of thin film fuses are deposited on the printed circuit board, each fuse providing circuit protection to one of the plurality of conductive traces.

Claims

1. A method for manufacturing an electrical assembly comprised of an electrically insulating substrate having a conductive trace on a first surface thereof to define an electrical circuit geometry, the method comprising the following steps:

removing a portion of the conductive trace to expose the electrically insulating substrate and form first and second circuit traces;

depositing a first conductive layer on the exposed substrate, the first conductive layer electrically connecting the first and second circuit traces; and

depositing a second conductive layer on the first conductive layer to form a fusible link.

2. The method of claim 1 wherein the first conductive layer is comprised of a material other than a material comprising the second conductive layer.

3. The method of claim 1 including the step of applying a protective coating to the fusible link.

4. The method of claim 1 wherein the step of removing a portion of the conductive trace to expose the electrically insulating substrate and form first and second circuit traces further includes the steps of:

masking first and second portions of the conductive trace leaving a portion of the conductive trace unmasked;

removing the unmasked portion of the conductive trace to expose the insulating substrate; and

removing the masking from the first and second portions of the conductive trace to define the first and second circuit traces.

5. The method of claim 1 wherein the step of depositing a first conductive layer on the exposed substrate to electrically connect the first and second circuit traces further includes the steps of:

applying a conductive material to the exposed substrate and portions of the first and second circuit traces;

masking the conductive material;

leaving a portion of the conductive material unmasked; and

removing the unmasked conductive material to define first and second terminal pads and a fuse element.

6. The method of claim 1, wherein the first conductive layer is deposited on the exposed substrate by electroless plating.

7. The method of claim 1, wherein the first conductive layer comprises copper.

8. The method of claim 1 wherein the step of depositing a second conductive layer on the first conductive layer to form a fusible link further includes the steps of:

masking the first conductive layer and portions of the first and second circuit traces;

exposing a portion of the first conductive layer;

depositing the second conductive layer on the exposed portion of the first conductive layer; and

removing the masking from the first conductive layer and the portions of the first and second circuit traces.

9. A method for manufacturing an electrical assembly comprising an electrically insulating substrate and an integrated fuse, the method comprising the steps of:

conditioning the insulating substrate;

depositing a first conductive layer on the insulating substrate;

electrically connecting a first and a second conductive trace to the first conductive layer; and

applying a second conductive layer to the first conductive layer to form a fusible link.

10. The method of claim 9 further comprising the step of covering the fusible link with a protective coating.

11. The method of claim 9, wherein the first and second conductive traces are deposited on the insulating substrate, a portion of each of the first and second conductive traces being deposited on the first conductive layer.

12. The method of claim 11, wherein the first and second conductive traces have a thickness greater than a thickness of the first conductive layer.

13. The method of claim 9, wherein the first conductive layer is deposited on the insulating substrate by electroless plating.

14. The method of claim 13, wherein the first conductive layer is copper.

15. A method for manufacturing an electrical assembly comprised of an electrically insulating substrate having an electrical circuit geometry defined on a surface thereof, the method comprising the following steps:

providing an electrically insulating substrate having a first conductive layer attached to a first surface, the first conductive layer defining a desired circuit geometry;

creating first and second circuit traces in the first conductive layer;

creating a fusible element in the first conductive layer, the fusible element electrically connecting the first and second circuit traces; and

applying a second conductive layer to the first conductive layer to form a fusible link.

16. The method of claim 15, wherein the first conductive layer is comprised of a material selected from a group comprised of copper, silver, nickel, titanium, aluminum and alloys thereof.

17. The method of claim 15, wherein the second conductive layer is comprised of a material selected from a group comprised of tin, solder, lead and alloys thereof.

18. The method of claim 15, wherein the steps of creating the first and second circuit traces and the fusible element is carried out by:

masking portions of the first conductive layer; and

etching away the unmasked portions of the first conductive layer.

19. The method of claim 15 wherein the first and second circuit traces have a width, W₁, and the fusible element has a width, W₂, wherein W₁ is greater than W₂.