Trap and delay pulse generator for a high speed clock

• US 6,044,026 A
• Filed: 06/05/1998
• Issued: 03/28/2000
• Est. Priority Date: 06/05/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Morgan, Donald M.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/092,524
• Time in Patent Office: 662 Days
• Field of Search: 365/226, 365/233, 365/194, 365/230.08, 365/189.05, 365/191, 395/496, 326/93, 327/149, 327/153, 327/162
• US Class Current: 365/194
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A trap and delay pulse generator for command signals triggered off of a high speed clock allows a device to develop signals before initiating a function and to complete the function after the clock pulse expires and allows overlap of sequential functions. When a device receives a sequence of clock pulses triggering command signals it is necessary that the device complete the functions after the clock pulse expires before receiving a new command signal triggered off of a subsequent clock pulse. The trap and delay pulse generator latches the command signal triggered off of the clock pulse and delays it to ensure an operation is ready to proceed even if the clock signal expires before the present command is completed.

Claims

1. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:

an input stage for receiving a clock pulse;

an enable circuit coupled to the input stage for receiving and passing through the clock pulse when the device is to perform a function corresponding to the received clock pulse;

a latch circuit having a delay element coupled to the enable circuit for receiving the clock pulse provided by the enable circuit, wherein the clock pulse is delayed by a predetermined amount of time to ensure the device is configured for the function before initiating the function; and

a one-shot pulse generator coupled to the latch for receiving the latched clock pulse and generating an output pulse for initiation of the function;

wherein the latch circuit can be automatically reset.

5. The trap and delay pulse generator of claim 1 wherein the device is a synchronous dynamic random access memory (SDRAM).

6. The trap and delay pulse generator of claim 5 wherein the function is a READ command.

7. The trap and delay pulse generator of claim 1 further comprising a delay circuit coupled to the input stage for receiving and delaying the command signal to the enable circuit.

8. The trap and delay pulse generator of claim 7 wherein the delay circuit is adjustable.

2. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:

an input stage for receiving a clock pulse;

an enable circuit coupled to the input stage for receiving and passing through the clock pulse when the device is to perform a function corresponding to the received clock pulse;

a latch circuit having a delay element coupled to the enable circuit for receiving the clock pulse provided by the enable circuit, wherein the clock pulse is delayed by a predetermined amount of time to ensure the device is configured for the function before initiating the function;

a one-shot pulse generator coupled to the latch for receiving the latched clock pulse and generating an output pulse for initiation of the function; and

a pulse width circuit coupled to the one-shot pulse generator for adjusting a pulse width of the output pulse.

3. The trap and delay pulse generator of claim 2 wherein the pulse width is dependent upon the amount of time the clock pulse is latched by the latch circuit.

4. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:

an input stage for receiving a clock pulse;

an enable circuit coupled to the input stage for receiving and passing through the clock pulse when the device is to perform a function corresponding to the received clock pulse;

a latch circuit having a delay element coupled to the enable circuit for receiving the clock pulse provided by the enable circuit, wherein the clock pulse is delayed by a predetermined amount of time to ensure the device is configured for the function before initiating the function;

a one-shot pulse generator coupled to the latch for receiving the latched clock pulse and generating an output pulse for initiation of the function; and

a control input coupled to the one-shot pulse generator for inhibiting generation of the output pulse after the clock pulse has been latched if the new function is not to be performed.

9. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:

an input stage for receiving at least one clock pulse and generating an output clock signal;

an adjustable delay circuit coupled to the input stage for receiving the output clock signal and providing a delayed output signal on an output connection;

an enable circuit having a first input connection coupled to the output connection of the adjustable delay circuit, the enable circuit has a second input connection coupled to receive an enable signal;

a latch circuit having an input connection coupled to an output connection of the enable circuit; and

a one-shot pulse generator coupled to an output connection of the latch circuit to generate an output pulse.

10. The trap and delay pulse generator of claim 9 embodied in an integrated circuit and wherein the enable signal is active when the integrated circuit performs a specific operation.

11. The trap and delay pulse generator of claim 10 wherein the integrated circuit is a memory device and the specific operation is a read operation.

12. The trap and delay pulse generator of claim 9 wherein the adjustable delay circuit comprises a plurality of series coupled inverter circuits and a plurality of switches.

13. The trap and delay pulse generator of claim 9 wherein the enable circuit comprises a NAND gate.

14. The trap and delay pulse generator of claim 9 wherein the latch circuit comprises a pair of cross coupled NAND gates and a delay circuit coupled to an output connection of the cross coupled NAND gates.

15. The trap and delay pulse generator of claim 14 wherein the latch circuit further comprises

a pulse width test option circuit to widen a signal pulse provided by the one-shot pulse generator circuit.

16. The trap and delay pulse generator of claim 15 wherein the pulse width test option circuit comprises a plurality of controllable delay circuits coupled to receive an output from the delay circuit, the plurality of controllable delay circuits can be selectively activated in response to a test signal input.

17. The trap and delay pulse generator of claim 9 wherein the one-shot pulse generator comprises a NAND gate to receive first and second input signals, wherein the first and second input signals are complementary signals and the second input signal is delayed in time behind the first input signal.

18. The trap and delay pulse generator of claim 9 wherein the one-shot pulse generator comprises a NAND gate to receive first, second and third input signals, wherein the first and second input signals are complementary signals and the second input signal is delayed in time behind the first input signal, the third input signal is the enable signal.

19. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:

an input stage for receiving at least one clock pulse and generating an output clock signal;

an adjustable delay circuit coupled to the input stage for receiving the output clock signal and providing a delayed output signal on an output connection;

an enable circuit having comprising a first NAND gate having a first input connection coupled to the output connection of the adjustable delay circuit via an inverter circuit, the first NAND gate has a second input connection coupled to receive an enable signal;

a latch circuit comprising second and third cross-coupled NAND gates and a delay circuit coupled to an output connection of the cross coupled NAND gates, the latch circuit has an input connection coupled to an output connection of the enable circuit;

a first delay element coupled to an output connection of the cross coupled NAND gates;

a second delay element coupled to an output connection of the first delay element;

a logic gate coupled to an output connection of the second delay element; and

a one-shot pulse generator coupled to an output connection of the logic gate and the output of the first delay element.

20. The trap and delay pulse generator of claim 19 wherein the one-shot pulse generator is deactivated in response to the enable signal.

21. The trap and delay pulse generator of claim 19 wherein the logic gate is an inverter.

22. The trap and delay pulse generator of claim 19 wherein the logic gate is an NOR gate.

23. The trap and delay pulse generator of claim 19 embodied in an integrated circuit and wherein the enable signal is active when the integrated circuit performs a specific operation.

24. The trap and delay pulse generator of claim 23 wherein the integrated circuit is a memory device and the specific operation is a read operation.

25. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:

an input stage for receiving at least one clock pulse and generating an output clock signal;

an adjustable delay circuit coupled to the input stage for receiving the output clock signal and providing a delayed output signal on an output connection, the adjustable delay circuit comprises plurality of series coupled inverter circuits and a plurality of switches;

an enable circuit having comprising a first NAND gate having a first input connection coupled to the output connection of the adjustable delay circuit via an inverter circuit, the first NAND gate has a second input connection coupled to receive an enable signal;

a latch circuit comprising second and third cross-coupled NAND gates and a delay circuit coupled to an output connection of the cross coupled NAND gates, the latch circuit has an input connection coupled to an output connection of the enable circuit;

a first delay element coupled to an output connection of the cross coupled NAND gates;

a pulse width test option circuit coupled to an output connection of the first delay element; and

a one-shot pulse generator coupled to an output connection of the pulse width test option circuit and the output of the first delay element.

26. The trap and delay pulse generator of claim 25 wherein the pulse width test option circuit comprises a plurality of controllable delay circuits coupled to receive the output connection of the first delay element, the plurality of controllable delay circuits can be selectively activated in response to a test signal input.

27. The trap and delay pulse generator of claim 25 wherein the one-shot pulse generator is deactivated in response to the enable signal.

28. The trap and delay pulse generator of claim 25 embodied in an integrated circuit and wherein the enable signal is active when the integrated circuit performs a specific operation.

29. The trap and delay pulse generator of claim 28 wherein the integrated circuit is a memory device and the specific operation is a read operation.