Trap and delay pulse generator for a high speed clock
First Claim
1. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:
- an input stage for receiving a clock pulse;
an enable circuit coupled to the input stage for receiving and passing through the clock pulse when the device is to perform a function corresponding to the received clock pulse;
a latch circuit having a delay element coupled to the enable circuit for receiving the clock pulse provided by the enable circuit, wherein the clock pulse is delayed by a predetermined amount of time to ensure the device is configured for the function before initiating the function; and
a one-shot pulse generator coupled to the latch for receiving the latched clock pulse and generating an output pulse for initiation of the function;
wherein the latch circuit can be automatically reset.
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Accused Products
Abstract
A trap and delay pulse generator for command signals triggered off of a high speed clock allows a device to develop signals before initiating a function and to complete the function after the clock pulse expires and allows overlap of sequential functions. When a device receives a sequence of clock pulses triggering command signals it is necessary that the device complete the functions after the clock pulse expires before receiving a new command signal triggered off of a subsequent clock pulse. The trap and delay pulse generator latches the command signal triggered off of the clock pulse and delays it to ensure an operation is ready to proceed even if the clock signal expires before the present command is completed.
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Citations
29 Claims
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1. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:
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an input stage for receiving a clock pulse; an enable circuit coupled to the input stage for receiving and passing through the clock pulse when the device is to perform a function corresponding to the received clock pulse; a latch circuit having a delay element coupled to the enable circuit for receiving the clock pulse provided by the enable circuit, wherein the clock pulse is delayed by a predetermined amount of time to ensure the device is configured for the function before initiating the function; and a one-shot pulse generator coupled to the latch for receiving the latched clock pulse and generating an output pulse for initiation of the function; wherein the latch circuit can be automatically reset. - View Dependent Claims (5, 6, 7, 8)
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2. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:
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an input stage for receiving a clock pulse; an enable circuit coupled to the input stage for receiving and passing through the clock pulse when the device is to perform a function corresponding to the received clock pulse; a latch circuit having a delay element coupled to the enable circuit for receiving the clock pulse provided by the enable circuit, wherein the clock pulse is delayed by a predetermined amount of time to ensure the device is configured for the function before initiating the function; a one-shot pulse generator coupled to the latch for receiving the latched clock pulse and generating an output pulse for initiation of the function; and a pulse width circuit coupled to the one-shot pulse generator for adjusting a pulse width of the output pulse. - View Dependent Claims (3)
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4. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:
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an input stage for receiving a clock pulse; an enable circuit coupled to the input stage for receiving and passing through the clock pulse when the device is to perform a function corresponding to the received clock pulse; a latch circuit having a delay element coupled to the enable circuit for receiving the clock pulse provided by the enable circuit, wherein the clock pulse is delayed by a predetermined amount of time to ensure the device is configured for the function before initiating the function; a one-shot pulse generator coupled to the latch for receiving the latched clock pulse and generating an output pulse for initiation of the function; and a control input coupled to the one-shot pulse generator for inhibiting generation of the output pulse after the clock pulse has been latched if the new function is not to be performed.
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9. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:
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an input stage for receiving at least one clock pulse and generating an output clock signal; an adjustable delay circuit coupled to the input stage for receiving the output clock signal and providing a delayed output signal on an output connection; an enable circuit having a first input connection coupled to the output connection of the adjustable delay circuit, the enable circuit has a second input connection coupled to receive an enable signal; a latch circuit having an input connection coupled to an output connection of the enable circuit; and a one-shot pulse generator coupled to an output connection of the latch circuit to generate an output pulse. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:
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an input stage for receiving at least one clock pulse and generating an output clock signal; an adjustable delay circuit coupled to the input stage for receiving the output clock signal and providing a delayed output signal on an output connection; an enable circuit having comprising a first NAND gate having a first input connection coupled to the output connection of the adjustable delay circuit via an inverter circuit, the first NAND gate has a second input connection coupled to receive an enable signal; a latch circuit comprising second and third cross-coupled NAND gates and a delay circuit coupled to an output connection of the cross coupled NAND gates, the latch circuit has an input connection coupled to an output connection of the enable circuit; a first delay element coupled to an output connection of the cross coupled NAND gates; a second delay element coupled to an output connection of the first delay element; a logic gate coupled to an output connection of the second delay element; and a one-shot pulse generator coupled to an output connection of the logic gate and the output of the first delay element. - View Dependent Claims (20, 21, 22, 23, 24)
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25. A trap and delay pulse generator for a device receiving a series of clock pulses comprising:
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an input stage for receiving at least one clock pulse and generating an output clock signal; an adjustable delay circuit coupled to the input stage for receiving the output clock signal and providing a delayed output signal on an output connection, the adjustable delay circuit comprises plurality of series coupled inverter circuits and a plurality of switches; an enable circuit having comprising a first NAND gate having a first input connection coupled to the output connection of the adjustable delay circuit via an inverter circuit, the first NAND gate has a second input connection coupled to receive an enable signal; a latch circuit comprising second and third cross-coupled NAND gates and a delay circuit coupled to an output connection of the cross coupled NAND gates, the latch circuit has an input connection coupled to an output connection of the enable circuit; a first delay element coupled to an output connection of the cross coupled NAND gates; a pulse width test option circuit coupled to an output connection of the first delay element; and a one-shot pulse generator coupled to an output connection of the pulse width test option circuit and the output of the first delay element. - View Dependent Claims (26, 27, 28, 29)
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Specification