Semiconductor storage device and electronic equipment using the same

• US 6,044,028 A
• Filed: 07/14/1997
• Issued: 03/28/2000
• Est. Priority Date: 10/16/1995
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Kumagai, Takashi, Tomohiro, Yasuhiko
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/891,822
• Time in Patent Office: 988 Days
• Field of Search: 365/200, 365/230.03, 365/203, 365/230.01, 365/230.06
• US Class Current: 365/200
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A semiconductor storage device which can prevent a short-circuit current from flowing therethrough even if a short circuit occurs between main word lines and bit lines. The semiconductor storage device has a plurality of normal memory cell array blocks, each including multiple columns of bit line pairs, sub word lines and normal memory cells. The semiconductor storage device also includes main word lines extending through the plurality of normal memory cell array blocks, a main row selecting decoder for selecting one of the main word lines on the basis of a main row address signal, a sub row selecting decoder for selecting one of the sub word lines depending on one of the main word lines on the basis of a sub row address signal, and a pre-charge circuit for pre-charging a pair of bit lines. The main row selecting decoder has a first setting circuit for inactivating the main word line at a high level potential substantially equal to a potential of a pre-charged bit line pair, while at a low level potential, the main word line is activated. The sub row selecting decoder has a second setting circuit for inactivating the sub word lines when the main word line is in the high level potential. The second setting circuit has an inverting element for receiving and inverting a signal from the main word line, the inverted signal being then outputted therefrom, and a switch for inactivating the sub word lines when the output of the inverting element is in the low level potential.

Claims

1. A semiconductor storage device comprising;

a plurality of normal memory cell array blocks, each of the normal memory cell array blocks including multiple columns of bit line pairs, rows of sub word lines and a plurality of normal memory cells disposed at respective intersections between said multiple columns of bit line pairs and said N×

n rows of sub word lines, said sub word lines being divided into a plurality of blocks in a column direction;

N rows of main word lines extending through said plurality of memory cell array blocks, wherein n of said sub word lines depending on one of said main word lines come into a selectable state by activating said one of said main word lines;

main row selecting means used by all of said normal memory cell array blocks for selecting one of said main word lines on the basis of a main row address signal;

block selecting means, each of the block selecting means provided for one of said normal memory cell array blocks, for outputting a sub row address signal for selecting one of said sub word lines within corresponding one of said normal memory cell array blocks on the basis of a block address signal;

sub row selecting means, each of the sub row selecting means provided for one of said normal memory cell array blocks, for selecting one of said n sub word lines depending on one of said main word lines selected based on said main row address signal on the basis of said sub row address signal; and

pre-charge means for pre-charging one of said multiple columns of bit line pairs;

wherein said main row selecting means activates and selects one of said main word lines at a low potential level and inactivates the other main word lines at a high potential level, said high potential level being substantially equal to a potential level of a pre-charged bit line pair of said plural columns of bit line pairs, wherein said main row selecting means includes a first setting means for activating and selecting one of said main word lines at a low potential level and for inactivating the other main word lines at a high potential level, said high potential level being substantially equal to a potential level of said pre-charged bit line pair;

said sub row selecting means includes a second setting means, disposed between one of said main word lines and one of said sub word lines, for inactivating said one of said sub word lines when said one of said main word lines is at a high potential level; and

said second setting means includes;

an inverting element which receives a signal from said one of said main word lines to invert and output a received signal; and

switch means for activating said one of said sub word lines when an output of said inverting element is at a low potential level.

2. The semiconductor storage device as defined in claim 1, further including at least one sub row address signal line which is connected between said sub row selecting means and said block selecting means to be activated by said sub row address signal;

and

wherein said switch means includes;

a first switch for activating said one of said sub word lines when said one of said main word lines and said at least one sub row address signal line are active; and

a second switch for lowering the potential of said one of said sub word lines to a ground potential to inactivate said one of said sub word lines on the basis of an output of said inverting element when said one of said main word lines is inactive.

3. The semiconductor storage device as defined in claim 2, wherein said first switch is formed by a transmission gate disposed between said one of said sub word lines and said at least one sub row address signal line;

and

a first control terminal and a second control terminal of said transmission gate are connected to said one of said main word lines and the output of said inverting element, respectively, for controlling a continuity between said one of said sub word lines and said at least one sub row address signal line.

4. The semiconductor storage device as defined in claim 3, wherein said second switch is a switching element which is connected between said one of said sub word lines and a ground line and controlled by the output of said inverting element.

5. The semiconductor storage device as defined in claim 1, further including at least one sub row address signal line which is connected between said sub row selecting means and said block selecting means to be activated by said sub row address signal;

and

wherein said second setting means has gate means for receiving an output of said at least one sub row address signal line and the output of said inverting element, and activating said one of said sub word lines when said one of said main word lines and said at least one sub row address signal line depending on said one of said main word lines are active, and inactivating said one of said word lines when said one of said main word lines is inactive.

9. The semiconductor storage device as defined in claim 1, further including an insulation film which is interposed between said multiple columns of bit line pairs and said N rows of main word lines.

10. An electronic equipment having the semiconductor storage device as defined in claim 1.

6. A semiconductor storage device comprising:

a plurality of normal memory cell array blocks, each of the normal memory cell array blocks including multiple columns of bit line pairs, N×

n rows of sub word lines and a plurality of normal memory cells disposed at respective intersections between said plural columns of bit line pairs and said N×

n rows of sub word lines, said sub word lines being divided into a plurality of blocks in a column direction;

redundancy memory cell array blocks, each of the redundancy memory cell array blocks is provided for one of said normal memory cell array blocks, and has a redundancy memory cell which can be substituted for any failed one of said normal memory cells;

N rows of main word lines extending through said plurality of normal memory cell array blocks and said redundancy memory cell array blocks, wherein n of said sub word lines depending on one of said main word lines come into a selectable state by activating said one of said main word lines;

main row selecting means which is used by all of said normal memory cell array blocks for selecting one of said main word lines by setting a potential of said one of said main word lines at a high potential level on the basis of a main row address signal;

block selecting means, each of the block selecting means provided for one of said normal memory cell array blocks, for outputting a sub row address signal for selecting one of said sub word lines within corresponding one of said normal memory cell array blocks on the basis of a block address signal;

sub row selecting means, each of the sub row selecting means provided for one of said normal memory cell array blocks, for selecting one of said n sub word lines depending on one of said main word lines selected by said main row address signal on the basis of said sub row address signal;

pre-charge means for pre-charging one of said multiple columns of bit line pairs; and

at least one sub row address signal line which is connected between said sub row selecting means and said block selecting means to be activated by said sub row address signal;

wherein said block selecting means has change means for changing a failed one of said normal memory cells for a redundancy memory cell in said redundancy memory cell array block in response to a redundancy selection signal used for selecting said redundancy memory cell;

wherein said main row selecting means has potential setting means for setting a potential of one of said main word lines used to select a failed one of said normal memory cells at a high potential level substantially equal to a potential level of pre-charged one of said bit line pairs at all times when said change means changes the failed one of said normal memory cells for said redundancy memory cell;

said sub row selecting means has control means, responsive to an inhibiting signal activated when the selection of the failed one of said normal memory cells is inhibited, to inactivate n of said sub word lines connected to the failed one of said failed normal memory cells; and

said potential setting means includes;

first potential setting means for setting a potential of said one of said main word lines substantially equal to a potential of pre-charged one of said bit line pairs always at a time of changing by said change means;

second potential setting means for setting one of said main word lines to a high potential level based on an output of said main row address signal to make said normal memory cells to come into a selectable state before the changing by said change means; and

switchover means for performing the switching of said first potential setting means and said second potential setting means from one to another.

7. The semiconductor storage device as defined in claim 6, further including at least one main row address signal line which is connected to said main row selecting means and activated by said main row address signal;

and

wherein said switchover means has a programming element interposed and connected between a ground line and a first power source;

wherein said second potential setting means includes a first switch which is disposed between a second power source and one of said main word lines, the first switch includes a first control terminal, the first control terminal of said first switch being connected to said programming element; and

wherein said first potential setting means includes a second switch which is disposed between said at least one main row address signal line and said one of said main word lines, the second switch includes a second control terminal, the second control terminal of said second switch being connected to said programming element.

8. The semiconductor storage device as defined in claim 6, wherein said control means includes gate means, disposed between one of said main word lines and one of said sub word lines, for inactivating said one of said sub word lines independently of a logic of said sub row address signal when said inhibiting signal is active.

11. The semiconductor storage device as defined in claim 6, further including an insulation film which is interposed between said multiple columns of bit line pairs and said N rows of main word lines.

12. An electronic equipment having the semiconductor storage device as defined in claim 6.