Incremental critical area computation for VLSI yield prediction

• US 6,044,208 A
• Filed: 04/30/1998
• Issued: 03/28/2000
• Est. Priority Date: 04/30/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Lavin, Mark Alan, Papadopoulou, Evanthia
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US09/070,834
• Time in Patent Office: 698 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 395/500.2, 395/500.05, 395/500.06
• US Class Current: 716/52
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An efficient method to compute critical area for shorts and breaks in rectilinear layouts in Very Large Scale Integrated (VLSI) circuits. The method is incremental and works in the L.sub.∞ geometry and has three major steps: Compute critical area for rectilinear layouts for both extra material and missing material defects (i.e., shorts and opens) by modeling defects as squares (which corresponds to the L.sub.∞ metric) instead of circles (Euclidean geometry). Treat the critical region for shorts and opens between any two edges or corners of the layout as a rectangle that grows uniformly as the defect radius increases. This is valid for rectilinear layouts and square defects (L.sub.∞ metric) . Use an incremental critical area algorithm for shorts and opens, which are computed for rectilinear layouts assuming square defects. Non-rectilinear layouts are approximated, first, by a rectilinear layout using a shape processing tool. The critical area for the rectilinear approximation is computed using the preferred incremental method.

Claims

1. A computer implemented method for critical area computation of defects in VLSI circuit manufacturing comprising the steps of:

a) retrieving a design layer containing a plurality of design shapes;

b) retrieving a list of defect sizes ordered in increasing size;

c) determining seed critical regions for said design layer;

d) listing said determined seed critical regions in an ordered list in order of increasing critical radius;

e) identifying all seed critical regions having a critical radius less than a minimum defect size and removing each said identified seed critical region from said ordered list; and

f) generating an actual critical region for each said identified seed critical region.

2. The computer implemented method of claim 1 wherein the step (f) of generating an actual critical region comprises expanding each identified seed critical region by the difference between its critical radius and the critical radius of said minimum defect size, said generated actual critical region being rectangular.

3. The computer implemented method of claim 1 further comprising the steps of:

g) identifying all seed critical regions having a critical radius less than a next smallest defect size and removing each said identified seed critical region from said ordered list, said next smallest defect size being identified as a current defect size;

h) generating an actual critical region for each said identified seed critical region;

i) generating additional critical region by expanding the critical region of the previous defect size by the difference between said current defect size and said previous defect size; and

j) repeating steps (g) through (i) for all listed defect sizes.

4. The computer implemented method of claim 3 wherein the step (a) of retrieving a design layer further comprises unioning overlapping shapes in the design layer.

5. The computer implemented method of claim 4 wherein the step (b) of determining seed critical regions comprises the steps of:

1) determining all horizontal seed critical regions; and

,

2) determining all vertical seed critical regions.

6. A method of integrated circuit chip design including checking the design according to the computer implemented method of claim 1 and further comprising the step of:

g) modifying a design layer of said checked design based on said generated actual critical region to improve manufacturing yield; and

h) rechecking said design using said computer implemented method.

7. A method of integrated circuit chip design according to claim 6 further comprising repeating steps (g) and (h) until a desired predicted yield is achieved.

8. A system for analyzing defect critical areas of integrated circuit chips, said system comprising:

means for storing a plurality of design shapes on a design layer;

means for determining seed critical regions for said stored design shapes;

means for organizing said determined seed critical regions according to a critical radius;

means for selectively eliminating all seed critical regions less than a minimum defect size; and

means for generating an actual critical region for each remaining said seed critical region.

9. A system for analyzing defect critical areas integrated circuit chips as in claim 8, further comprising means for expanding each identified seed critical region according to the difference between a critical radius of said identified seed critical region and the critical radius of said minimum defect size.

10. A system for analyzing defect critical areas integrated circuit chips as in claim 8, further comprising means for unioning overlapping shapes in the design layer.