Method for graphically representing a digital device as a behavioral description with data and control flow elements, and for converting the behavioral description to a structural description

• US 6,044,211 A
• Filed: 03/14/1994
• Issued: 03/28/2000
• Est. Priority Date: 03/14/1994
• Status: Expired due to Fees

• Current Assignee: Advanced Data Controls Corp.
• Original Assignee: C.A.E. Plus, Inc.
• Inventors: Jain, Prem P.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): JONES, HUGH M
• Application Number:
  US08/212,908
• Time in Patent Office: 2,206 Days
• Field of Search: 364/488, 364/489, 364/490, 364/578, 395/500, 395/500.19
• US Class Current: 716/102
• CPC Class Codes: G06F 8/34 Graphical or visual programming
• CPC Class Codes: G06F 9/4498 Finite state machines

Abstract

A computer-aided synthesis and verification tool is provided for modeling a digital device at a behavioral level and for synthesizing to a structural level utilizing user-defined attributes. The behavioral level is represented as a Data Dependency Graph (DDG) having a plurality of operations (shown as nodes) and operands (shown as arcs) which connect the nodes. Each operation or node is represented as a graphical icon, wherein the icon can have user-defined attributes associated with it. The attributes, nodes, and arcs are compiled and reduced to a Register Transfer Level (RTL) simulation model compatible with present VHDL and Verilog formats. Conversion from a behavioral model to an RTL model includes monitoring the internal states at rising clock edges and constructing states, events and event transistions (i.e., control path information) for each data value in the matrix of values within the data path. The resulting RTL model therefore includes both control path information and data path information, and can be further reduced to technology dependent or silicon dependent circuits or structures.

Claims

1. A method for graphically designing a digital device, comprising the steps of:

identifying a fixed and limited number of descriptors which behaviorally describe any digital device to be designed;

placing symbolic icons representing at least two of said descriptors upon a graphic display and operationally connecting said icons with an arc placed therebetween; and

using a pull-down menu activated from said placed icons, thereafter defining a list of attributes to said icons, wherein said attributes include both data path and control path information for a digital device graphically designed from said placed icons.

2. The method as recited in claim 1, wherein each said symbolic icon is configured as a node upon said graphic display, said icon is selectable after placement on said display and, after selection, said icon includes a menu-driven node form adapted for receiving user input of said attributes.

3. The method as recited in claim 1, wherein said data path information comprises hardware component type, input/output ports for said component type, and functionality for said component type.

4. The method as recited in claim 1, wherein said data path information comprises a software module, input/output parameters of the software module, and functionality of the module.

5. The method as recited in claim 1, wherein said control path information comprises timing of signals sent to said data path and operation priority of hardware component arranged within said data path.

6. The method as recited in claim 1, wherein said control path information comprises an enable signal sent to said data path and operation priority of a software module arranged within said data path.

7. The method as recited in claim 1, further comprising:

applying a sequence of simulation vectors to the graphically modeled said digital device and monitoring the output of a first icon to produce a sequence of output values; and

verifying the accuracy of said graphically modeled said digital device by reading said sequence of output values and comparing said sequence of output values against a user-defined sequence of expected values.

8. The method as recited in claim 7, wherein said applying step comprises stimulating a netlist of data values representing said graphically modeled said digital device.

9. The method as recited in claim 7, wherein said applying step further comprises monitoring the output of a select set of icons at rising edges of a clocking signal to determine events at said set of icons and transitions of said events between said rising edges of the clocking signal.

10. The method as recited in claim 9, wherein said events and transitions of said events comprise a finite state machine representative of control path information for said digital device.

11. A method for capturing a digital device as a behavioral description and for converting the behavioral description to a structural description, said method comprising the steps of:

constructing a behavioral description of a digital device upon a graphic display by graphically connecting a set of symbolic icons drawn from a fixed number of icons contained within an icon library having fewer than fifteen icons;

mapping user-defined inputs to each of said symbolic icons to define a graphical model having data path attributes of said digital device;

representing said graphical model as a matrix of data values corresponding to binary values at a plurality of internal states within said graphical model;

applying a set of input values to said matrix of data values to modify said matrix and, simultaneous with rising edges of a clocking signal, monitoring the modified said matrix at select said internal states;

determining events at the select said internal states, and determining transitions of said events at said internal states between said rising edges of the clocking cycle; and

combining events and transitions of events to produce a finite state machine having control path information, and merging said control path information with said data path attributes to produce a structural description of said digital device.

12. The method as recited in claim 11, wherein said structural description is described in RTL form and in an HDL language.

13. The method as recited in claim 11, wherein said structural description is described as interconnection of software modules, wherein said software modules represent software operation and are represented in programming language.

14. The method as recited in claim 11, wherein said mapping step comprises selecting an icon configured on said display and activating a pull-down menu from the selected said icon, wherein said pull-down menu is adapted to receive said user-defined inputs.

15. The method as recited in claim 14, wherein said pull-down menu is designed to receive inputs from a parts library comprising functions from a function library, hardware instances, input and output ports for each said instance, and timing priority.

16. The method as recited in claim 11, wherein said set of symbolic icons comprise fewer than fifteen symbolic icons capable of representing each and every possible behavioral description of said digital device.

17. The method as recited in claim 11, wherein one of said set of symbolic icons represents a pipeline icon.

18. The method as recited in claim 11, wherein said applying step further comprises applying a subsequent sequence of input values after said sequence of input values have been fully applied.

19. The method as recited in claim 11, wherein said data path attributes comprise a data path of hardware components and transfer signals sent between said components, and wherein said control path information comprises a control path of finite states for each of said hardware components and control logic for timed operation of said components.

20. The method as recited in claim 19, wherein said hardware components comprise registers.

21. The method as recited in claim 19, wherein said control logic comprises tri-state and multiplex (MUX) components.

22. The method as recited in claim 11, wherein each data value within said matrix of data values is modified before said data value receives a subsequent input value within said set of input values.

23. The method as recited in claim 11, wherein modifications to said matrix of data values are presented upon said graphic display as said events at a time selected by a user.

24. The method as recited in claim 11, wherein modifications to said matrix of data values are presented upon said graphic display as a timed event.

25. A method for capturing a digital device as a behavioral description, for converting the behavioral description to a structural description, and for verifying the behavioral and structural descriptions of said digital device, said method comprising the steps of:

providing a library of less than fifteen descriptors which behaviorally describe any digital device to be modeled;

placing symbolic icons representing at least two of said descriptors upon a graphic display and operationally connecting said icons with an arc to produce a behavioral description of a digital device;

using a pull-down menu activated from selection of said placed icons, mapping entries made by a user to said pull-down menu to define a graphical model having data path attributes of said digital device;

representing said graphic model as a matrix of data values corresponding to binary values at a plurality of internal states and an output state of said graphical model;

applying a set of input values to said matrix of data values to modify said matrix and produce a sequence of output values;

monitoring said a sequence of output values at the output state of said graphical model and, simultaneous with rising edges of a clocking signal, monitoring a resulting sequence of output values at select said internal states of said graphical model;

determining events at the select said internal states, and determining transistions of said events at said internal states between said rising edges of the clocking cycle;

combining events and transitions of events to produce a finite state machine having control path information, and merging said control path information with said data path attributes to produce a structural description of said digital device;

representing said structural description as a matrix of register-transfer level (RTL) data values corresponding to binary values at said output state; and

verifying the accuracy of said structural description by comparing the output values at the output state resulting from said applying step with the output values at the output state resulting from said representing step.