Dual clock power conservation system and method for timing synchronous communications
First Claim
1. In a wireless network of communicating player units having a predetermined rest interval between player unit communications, wherein the rest interval includes a predetermined first wait time and a predetermined second wait time, significantly longer than the first wait time, a system for a player unit to conserve power between communications comprising:
- a high speed clock having an input to energize said high speed clock, and an output operatively connected to communication circuits to provide a high speed clock period, T1, whereby said clock is used to execute procedures during a communication;
a low speed clock with a rate of power consumption that is low compared to said high speed clock, and having an output to provide a low speed clock period T2 ;
a first counter circuit having a first input operatively connected to said high speed clock output to determine the first waiting time by counting a predetermined number, n1, of high speed clock periods, said first counter circuit having an output to provide a first wait time signal after the first wait time is counted;
a second counter circuit having an input operatively connected to said low speed clock output to determine the second wait time by counting a predetermined number, n2 of low speed clock periods, said second counter circuit having an output to provide a second wait time signal after the second wait time is counted;
a power controller circuit having a first input operatively connected to said first counter circuit output, a second input operatively connected to said second counter circuit output, and an output operatively connected to said high speed clock input, to de-energize said high speed clock during the counting of the second wait time, and to energize said high speed clock when the second wait time signal is received, whereby the rest interval is precisely timed despite said high speed clock being de-energized for a majority of the rest interval.
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Accused Products
Abstract
A system is provided to time the periods of known inactivity in a synchronous communications system in such a manner as to allow the high speed oscillator, used in the various timing, modulation, and demodulation operations of a portable communications unit, to be shut off without a significant loss in timing resolution. A low power, low speed, oscillator is used to measure a majority of the inactive period to save battery power. The low speed oscillator has a frequency too slow to provide the resolution necessary for accurate timing. However, a small portion of the inactive period is timed with the high frequency oscillator. The fine resolution of the time segment measured by the high speed oscillator, when combined with segment of time measured by the low speed oscillator, yields a measurement of the inactive period that is approximately the same as obtained when just the high speed oscillator is used. A method of turning off a high speed oscillator in the timing of an inactive period between communications in a synchronous communications system is also provided for the purpose of conserving battery power.
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Citations
9 Claims
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1. In a wireless network of communicating player units having a predetermined rest interval between player unit communications, wherein the rest interval includes a predetermined first wait time and a predetermined second wait time, significantly longer than the first wait time, a system for a player unit to conserve power between communications comprising:
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a high speed clock having an input to energize said high speed clock, and an output operatively connected to communication circuits to provide a high speed clock period, T1, whereby said clock is used to execute procedures during a communication; a low speed clock with a rate of power consumption that is low compared to said high speed clock, and having an output to provide a low speed clock period T2 ; a first counter circuit having a first input operatively connected to said high speed clock output to determine the first waiting time by counting a predetermined number, n1, of high speed clock periods, said first counter circuit having an output to provide a first wait time signal after the first wait time is counted; a second counter circuit having an input operatively connected to said low speed clock output to determine the second wait time by counting a predetermined number, n2 of low speed clock periods, said second counter circuit having an output to provide a second wait time signal after the second wait time is counted; a power controller circuit having a first input operatively connected to said first counter circuit output, a second input operatively connected to said second counter circuit output, and an output operatively connected to said high speed clock input, to de-energize said high speed clock during the counting of the second wait time, and to energize said high speed clock when the second wait time signal is received, whereby the rest interval is precisely timed despite said high speed clock being de-energized for a majority of the rest interval. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A power conservation system as in 1 further comprising:
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a reference clock having an output to provide a highly accurate, highly stable reference clock period; a timer controller having a first input operatively connected to said high speed clock output, a second input operatively connected to said low speed clock output, and a third input operatively connected to said reference clock output, said timer controller dividing the low speed clock period by the reference clock period to determine the actual period of the low speed clock, and dividing the high speed clock period by the reference clock period to determine the actual period of the high speed clock, said timer controller having an output to provide signals representing the values of n1, n2, and n3, whereby the calculation of the values for n1, n2, and n3 are adjusted in response to the high and low speed clock periods to maintain accurate timing of the rest interval. - View Dependent Claims (9)
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Specification