Memory handling system that backfills dual-port buffer from overflow buffer when dual-port buffer is no longer full

• US 6,044,419 A
• Filed: 09/30/1997
• Issued: 03/28/2000
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Case, Colyn, Hayek, George
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): WANG, ALBERT C
• Application Number:
  US08/941,169
• Time in Patent Office: 910 Days
• Field of Search: 395/877, 395/872, 395/873, 395/858, 710/52, 710/53, 710/57, 710/521
• US Class Current: 710/57
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence

Abstract

The present invention relates to a method and apparatus for buffering data. The apparatus stores information in a buffer. When the buffer is full, overflow data is stored in an overflow memory. As data is removed from the buffer, the overflow data is transferred from overflow memory to the buffer.

Claims

1. A memory handling system comprising:

a register coupled to a source of data;

a dual-port buffer to receive data;

a fill logic to determine when the dual-port buffer is full; and

a memory controller coupled to a single-port overflow memory by a bi-directional bus and to the register, the memory controller routing data from the register to the overflow memory when the fill logic determines that the dual-port buffer is full, back-filling the dual-port buffer with data from the overflow memory when the fill logic determines that the dual-port buffer is no longer full, and routing data from the register to the dual-port buffer when no back-filling is in progress and the fill logic determines that the dual-port buffer is not full.

2. The memory handling system of claim 1 wherein the dual-port buffer and fill logic are placed on an integrated circuit chip and the overflow memory is on a second integrated circuit chip.

3. The memory handling system of claim 1 further comprising:

a multiplexer directing data into said dual-port buffer from the register and the overflow memory, a select line of the multiplexer coupled to the fill logic.

4. The memory handling system of claim 1 wherein an output of the dual-port buffer is coupled to an input of a graphics card.

5. The memory handling system of claim 1 further comprising:

a mapping unit to map the data to discontiguous pages of the overflow memory.

6. The memory handling system of claim 1 wherein the dual-port buffer is a first-in first-out memory device.

7. A method for buffering data comprising:

receiving a data segment in a register from a source of data;

transferring the data segment from the register to a single-port overflow memory by a bi-directional bus if a dual-port buffer is full;

back-filling the dual-port buffer from the overflow memory if the dual-port buffer is no longer full; and

transferring the data segment from the register to the dual-port buffer if the dual-port buffer is not full and the dual-port buffer is not being back-filled.

8. The method of claim 7 further comprising directing the data segment from one of the register and the overflow memory to the dual-port buffer with a multiplexer.

9. The method of claim 8 further comprising sending a select register signal to the multiplexer if the dual-port buffer is not full and the dual-port buffer is not being back-filled, and sending a select overflow memory signal to the multiplexer otherwise.

10. The method of claim 8 further comprising comparing a buffer begin pointer and a buffer end pointer to determine if the dual-port buffer is full.

11. A graphics accelerator comprising:

a register coupled to a bi-directional system bus for receiving graphics data from a central processor;

a dual-port buffer to receive the graphics data on a first port and supply the graphics data to a graphics processor on a second port;

a fill logic to determine when the dual-port buffer is full; and

a memory controller coupled to a system memory by the bi-directional system bus and to the register, the memory controller routing the graphics data from the register to the system memory when the fill logic determines that the dual-port buffer is full, back-filling the dual-port buffer with the graphics data from the system memory when the fill logic determines that the dual-port buffer is no longer full, and routing the graphics data from the register to the dual-port buffer when no back-filling is in progress and the fill logic determines that the dual-port buffer is not full.

12. The graphics accelerator of claim 11 further comprising:

a multiplexer directing the graphics data into the dual-port buffer from the register and the system memory, a select line of the multiplexer coupled to the fill logic.

13. The graphics accelerator of claim 11 further comprising a mapping unit to map the graphics data to discontiguous pages of the system memory.

14. The graphics accelerator of claim 11 wherein the dual-port buffer is a first-in first-out memory device.

15. A memory handling system comprising:

a register for receiving a data segment from a source of data;

means for transferring the data segment from the register to a single-port overflow memory by a bi-directional bus if a dual-port buffer is full;

means for back-filling the dual-port buffer from the overflow memory if the dual-port buffer is no longer full; and

means for transferring the data segment from the register to the dual-port buffer if the dual-port buffer is not full and the dual-port buffer is not being back-filled.

16. The memory-handling system of claim 15 further comprising a multiplexer for directing the data segment from one of the register and the overflow memory to the dual-port buffer.

17. The memory handling system of claim 15 further comprising means for sending a select register signal to the multiplexer if the dual-port buffer is not full and the dual-port buffer is not being back-filled, and sending a select overflow memory signal to the multiplexer otherwise.

18. The memory handling system of claim 15 further comprising means for comparing a buffer begin pointer and a buffer end pointer to determine if the dual-port buffer is full.