Memory system having memory devices each including a programmable internal register

• US 6,044,426 A
• Filed: 01/29/1999
• Issued: 03/28/2000
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/239,522
• Time in Patent Office: 424 Days
• Field of Search: 710/104, 710/8, 710/9, 710/10, 711/170
• US Class Current: 710/104
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system having a plurality of memory devices, each having at least one memory array which includes a plurality of memory cells. The memory system comprises a bus, a controller, a first memory device, and a second memory device. The bus includes a plurality of sisal lines coupled to the plurality of memory devices. The bus provides a transaction request including identification information generated by the controller, to the plurality of memory devices. The first and second memory device each include a programmable register, interface circuitry, and comparison circuitry. The interface circuitry of each memory device may store a memory identification value to identify each memory device on the bus. The interface circuitry of each memory device is coupled to the bus to receive a transaction request. The comparison circuitry of each memory device is coupled to the programmable register and the interface circuitry to determine whether the identification information in the transaction request corresponds to the memory identification value wherein when the identification information corresponds to a memory identification value, that memory device responds to the transaction request.

Claims

1. A memory system having a plurality of memory devices, the memory system comprises:

a bus having a plurality of signal lines coupled to the plurality of memory devices, the bus provides a transaction request to the plurality of memory devices, wherein the transaction request includes identification information;

a controller, coupled to the bus, wherein the controller generates the transaction request;

a first memory device including;

a memory array which includes a plurality of memory cells;

a programmable register to store a first memory identification value to identify the first memory device on the bus;

interface circuitry, coupled to the bus, to receive a transaction request;

comparison circuitry, coupled to the programmable register and the interface circuitry of the first memory, to determine whether the identification information in the transaction request corresponds to the first memory identification value wherein when the identification information corresponds to the first memory identification value, the first memory device responds to the transaction request; and

a second memory device including;

a memory array which includes a plurality of memory cells;

a programmable register to store a second memory identification value which identifies the second memory device on the bus;

interface circuitry, coupled to the bus, to receive the transaction request;

comparison circuitry, coupled to the programmable register and the interface circuitry of the second memory device, to determine whether the identification information in the transaction request corresponds to the second memory identification value wherein when the identification information corresponds to the second memory identification value, the second memory device responds to the transaction request.

2. The memory system of claim 1 wherein the transaction request includes N bits of information and the bus includes M number of signal lines wherein M is substantially less than N and the transaction request is provided in packet form.

3. The memory system of claim 1 wherein the transaction request includes N bits of information and the bus includes M number of signal lines wherein M is substantially less than N.

4. The memory system of claim 1 wherein the transaction request includes control information, address information and data information, wherein the control, address and data information are time multiplexed over the bus.

5. The memory system of claim 1 wherein the first memory device and the second memory device each include clock receiver circuitry to receive a first external clock signal and a plurality of output drivers to output data synchronously with respect to the first external clock signal.

6. The memory system of claim 1 wherein the first memory device and the second memory device each include:

clock receiver circuitry to receive a first external clock signal and a second external signal; and

a plurality of output drivers to output data on the bus synchronously with respect to the first and second external clock signals, wherein a first portion of the data is output synchronously with respect to the first external clock signal and a second portion of the data is output synchronously with respect to the second external clock signal.

7. The memory system of claim 6 wherein the first and second memory devices each further include a delay locked loop which is coupled to the clock receiver circuitry to receive the first and second external clock signals and to generate a first internal clock signal using the first and second external clock signals, wherein the plurality of output drivers, in response to the first internal clock signal, output the first portion of the data on the bus.

8. The memory system of claim 7 wherein the first and the second external clock signals are complementary.

9. The memory system of claim 7 wherein the delay locked loop further generates a second internal clock signal, and the plurality of output drivers, in response to the second internal clock signal, output data on the bus and wherein the first and the second memory devices each further include a multiplexer coupled to the delay locked loop to receive the first and the second internal clock signals, the multiplexer includes a first input coupled to a first internal data bus line and a second input coupled to a second internal data bus line, wherein the multiplexer couples the first internal data bus line to an input of one of the plurality of output drivers in response to the first internal clock signal and couples the second internal data bus line to the input of the one of the plurality of output drivers in response to the second internal clock signal.

10. The memory system of claim 6 wherein the first and second memory devices each further include a first delay locked loop to generate a first internal clock signal and a second delay locked loop to generate a second internal clock signal wherein, in response to the first internal clock signal, the plurality of output drivers output the first portion of data on the bus, and in response to the second internal clock signal, the plurality of output drivers output the second portion of the data on the bus.

11. The memory system of claim 10 wherein the first delay locked loop in each memory device generates the first internal clock signal using the first and the second external clock signals.

12. The memory system of claim 11 wherein the first and the second external clock signals are complementary.

13. The memory system of claim 10 wherein the first memory device and second memory device each further include a programmable latency register to store a value which is representative of a number of clock cycles to transpire before the memory device responds to a read request wherein the plurality of output drivers output data on the bus in accordance with the value stored in the programmable latency register.

14. A system having a plurality of integrated circuit devices comprising:

a bus having a plurality of signal lines;

a master, coupled to the bus, to provide a transaction request to the devices, wherein the transaction request includes identification information;

a first integrated circuit device having at least one memory array which includes a plurality of memory cells, the first integrated circuit device being coupled to the bus to receive the transaction request, the first device includes;

a programmable register to store a first device identification value to identify the first integrated circuit device on the bus;

comparison circuitry, coupled to the programmable register, to determine whether the identification information in the transaction request corresponds to the first device identification value wherein when the identification information corresponds to the first device identification value, the first integrated circuit device interprets the transaction request; and

a second integrated circuit device having at least one memory array which includes a plurality of memory cells, the second integrated circuit device being coupled to the bus to receive the transaction request, the second integrated circuit device includes;

a programmable register to store a second device identification value to identify the second integrated circuit device on the bus;

comparison circuitry, coupled to the programmable register, to determine whether the identification information in the transaction request corresponds to the second device identification value wherein when the identification information corresponds to the second device identification value, the second integrated circuit device interprets the transaction request.

15. The system of claim 14 wherein the transaction request includes N bits of information and the bus includes M number of signal lines wherein M is substantially less than N and the transaction request is provided in packet form.

16. The system of claim 15 wherein the transaction request includes control information address information and data information, wherein the control, address and data information are time multiplexed over the bus.

17. The system of claim 14 wherein the first integrated circuit device and the second integrated circuit device each further include:

clock circuitry, coupled to the bus, to receive a first external clock signal, and

a plurality of output drivers to output data synchronously with respect to the first external clock signal.

18. The system of claim 17 wherein the first integrated circuit device and the second integrated circuit device each further include a plurality of input receivers to latch data synchronously with respect to the first external clock signal.

19. The system of claim 14 wherein the first integrated circuit device and the second integrated circuit device each further include:

clock circuitry, coupled to the bus, to receive first and second external clock signals, and

a plurality of output drivers, each output driver being coupled to the bus, to output data synchronously with respect to the first and the second external clock signals, wherein a first portion of the data is output synchronously with respect to the first external clock signal and a second portion of the data is output synchronously with respect to the second external clock signal.

20. The system of claim 19 wherein the first integrated circuit device and the second integrated circuit device each further include a plurality of input receivers to input data synchronously with respect to the first and the second external clock signals, wherein a first portion of the data is input synchronously with respect to the first external clock signal and a second portion of the data is input synchronously with respect to the second external clock signal.

21. A system having a plurality of integrated circuit devices comprising:

a bus having a plurality of signal lines for transceiving low voltage swing signals;

a master, coupled to the bus, to provide a transaction request to the integrated circuit devices, wherein the transaction request includes identification, control and address signals having a low voltage swing;

a first integrated circuit device including;

interface circuitry coupled to the bus, to receive the transaction request;

a programmable register coupled to the interface circuitry, to store a first device identification value to identify the first integrated circuit device on the bus;

comparison circuitry, coupled to the programmable register, to determine whether the identification signal in the transaction request corresponds to the first device identification value wherein when the identification signal corresponds to the first device identification value, the first integrated circuit device interprets the transaction request; and

a second integrated circuit device including;

interface circuitry coupled to the bus, to receive the transaction request;

a programmable register coupled to the interface circuitry, to store a second device identification value to identify the second integrated circuit device on the bus;

comparison circuitry, coupled to the programmable register, to determine whether the identification signal in the transaction request corresponds to the second device identification value wherein when the identification signal corresponds to the second device identification value, the second integrated circuit device interprets the transaction request.

22. The system of claim 21 wherein the low voltage swing is more than 250 millivolts and less than a full value CMOS logic swing.

23. The system of claim 22 wherein the full value CMOS logic swing is less than or equal to V_DD.

24. The system of claim 21 wherein the first integrated circuit device and the second integrated circuit device each further include:

clock circuitry, coupled to the bus, to receive a first external clock signal, and

a plurality of output drivers to output data synchronously with respect to the first external clock signal.

25. The system of claim 24 wherein the first integrated circuit device and the second integrated circuit device each further include a plurality of input receivers to latch data synchronously with respect to the first external clock signal.

26. The system of claim 25, wherein the plurality of input receivers generate full value CMOS logic swing signals.

27. The system of claim 21 wherein the first integrated circuit device and the second integrated circuit device each further include:

clock circuitry, coupled to the bus, to receive first and second external clock signals, and

a plurality of output drivers, each output driver being coupled to the bus, to output data synchronously with respect to the first and the second external clock signals, wherein a first portion of the data is output synchronously with respect to the first external clock signal and a second portion of the data is output synchronously with respect to the second external clock signal.

28. The system of claim 27 wherein the first integrated circuit device and the second integrated circuit device each further include a plurality of input receivers to latch data synchronously with respect to the first and the second external clock signals, wherein a first portion of the data is input synchronously with respect to the first external clock signal and a second portion of the data is input synchronously with respect to the second external clock signal.

29. The system of claim 21, wherein the plurality of signal lines are terminated using a plurality of resistors.