Configurable universal serial bus node

• US 6,044,428 A
• Filed: 03/17/1998
• Issued: 03/28/2000
• Est. Priority Date: 03/17/1998
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Rayabhari, Madhu
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US09/040,110
• Time in Patent Office: 742 Days
• Field of Search: 710/100, 710/101, 710/104, 710/63, 710/64, 710/72, 710/126, 710/129, 710/3, 710/128, 712/37, 345/156, 345/168, 709/231, 370/257, 370/364, 370/912, 455/6.3
• US Class Current: 710/305
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus

Abstract

A Universal Serial Bus node having a non-volatile memory is preprogrammed with the data bits necessary to configure an attached state machine to become a translator or modified translator for signals from a computer peripheral device. On startup, the Universal Serial Bus node is configured to translate signals to and from the computer peripheral device into USB protocol signals to and from a Universal Serial Bus equipped computer in order to assure proper communication therebetween.

Claims

1. A Universal Serial Bus node for a computer peripheral device to be used with a Universal Serial Bus equipped computer using the Universal Serial Bus standard, comprising:

a memory programmable with information related to the Universal Serial Bus and the computer peripheral device; and

circuitry connected to said memory responsive to said information for configuring said circuitry to have the capability of providing signals from the computer peripheral device to the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standards.

2. The Universal Serial Bus node as claimed in claim 1 wherein said circuitry is responsive to said information from said memory for configuring said circuitry to have the capability of responding to signals from the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standard.

3. The Universal Serial Bus node as claimed in claim 1 wherein said circuitry is responsive to said information from said memory for configuring said circuitry to have the capability of identifying the computer peripheral device to the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standard.

4. The Universal Serial Bus node as claimed in claim 1 wherein said memory is a non-volatile memory.

5. The Universal Serial Bus node as claimed in claim 1 wherein said circuitry is a state machine.

6. The Universal Serial Bus node as claimed in claim 1 including a computer peripheral device and wherein said memory is programmed to cause said circuitry to allow communication between said computer peripheral device and the Universal Serial Bus equipped computer.

7. The Universal Serial Bus node as claimed in claim 1 including a computer peripheral device and wherein said memory is programmed to cause said circuitry to modify communication between said computer peripheral device and the Universal Serial Bus equipped computer.

8. The Universal Serial Bus node as claimed in claim 1 including a computer peripheral device and a Universal Serial Bus equipped computer wherein:

said Universal Serial Bus equipped computer queries said computer peripheral device for identification;

said circuitry identifies said computer peripheral device to said Universal Serial Bus equipped computer;

said Universal Serial Bus equipped computer responds to said circuitry;

said circuitry responds to said computer peripheral device; and

said computer peripheral device providing signals for said circuitry to provide to said Universal Serial Bus equipped computer, all in conformance with the Universal Serial Bus standard.

9. A method for making a computer peripheral device useable with a Universal Serial Bus equipped computer using the Universal Serial Bus standard, comprising:

starting up a programmed memory having information related to the Universal Serial Bus standard and providing a configure signal related thereto; and

configuring circuitry connected to said memory for receiving said configure signal to be able to receive signals from the computer peripheral device and provide said signals to the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standard.

10. A Universal Serial Bus node for a computer peripheral device to be used with a Universal Serial Bus equipped computer using the Universal Serial Bus standard, comprising:

a non-volatile memory programmable with information related to the Universal Serial Bus and the computer peripheral device; and

a state machine connected to said memory responsive to said information for configuring said state machine to have the capability of providing signals from the computer peripheral device to the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standard.

11. The Universal Serial Bus node as claimed in claim 10 wherein said state machine is responsive to said information from said memory for configuring said state machine to have the capability of responding to signals from the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standard.

12. The Universal Serial Bus node as claimed in claim 10 wherein said state machine is responsive to said information from said memory for configuring said state machine to have the capability of identifying the computer peripheral device to the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standard.

13. The Universal Serial Bus node as claimed in claim 10 wherein said non-volatile memory is an EEPROM.

14. The Universal Serial Bus node as claimed in claim 10 wherein said non-volatile memory is a Flash memory.

15. The Universal Serial Bus node as claimed in claim 10 including a computer peripheral device and wherein said non-volatile memory is programmed to configure said state machine to allow communication between said computer peripheral device and the Universal Serial Bus equipped computer.

16. The Universal Serial Bus node as claimed in claim 10 including a computer peripheral device and wherein said non-volatile memory is programmed to configure said state machine to modify communications from said computer peripheral device and provide the modified communications between said computer peripheral device and the Universal Serial Bus equipped computer.

17. The Universal Serial Bus node as claimed in claim 10 wherein said computer peripheral device is a pointing device.

18. The Universal Serial Bus node as claimed in claim 10 wherein said computer peripheral device is a game peripheral.

19. The Universal Serial Bus node as claimed in claim 10 wherein said computer peripheral device is a multimedia peripheral.

20. The Universal Serial Bus node as claimed in claim 10 including a computer peripheral device and a Universal Serial Bus equipped computer wherein:

said Universal Serial Bus equipped computer queries said computer peripheral device for identification;

said state machine identifies said computer peripheral device to said Universal Serial Bus equipped computer;

said Universal Serial Bus equipped computer responds to said state machine;

said state machine responds to said computer peripheral device; and

said computer peripheral device providing signals for said state machine to provide to said Universal Serial Bus equipped computer, all in conformance with the Universal Serial Bus standard.

21. A method for making a computer peripheral device useable with a Universal Serial Bus equipped computer using the Universal Serial Bus standard, comprising:

starting up a programmed non-volatile memory having preprogrammed data bits related to the Universal Serial Bus standard for the computer peripheral device and providing said data bits for configuring a state machine; and

configuring said state machine to be able to provide and receive signals from the computer peripheral device, translate said signals into Universal Serial Bus signals to and from the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standard.

22. A Universal Serial Bus node for a computer peripheral device to be used with a Universal Serial Bus equipped computer using the Universal Serial Bus standard, comprising:

a non-volatile memory programmable with data bits related to the Universal Serial Bus and the computer peripheral device; and

a state machine connected to said memory responsive to said data bits for configuring said state machine to have the capability of translating signals from the computer peripheral device into Universal Serial Bus signals in conformance with the Universal Serial Bus standard to the Universal Serial Bus equipped computer and translating Universal Serial Bus signals from the Universal Serial Bus equipped computer to signals for the computer peripheral device.

23. The Universal Serial Bus node as claimed in claim 22 wherein said state machine is responsive to said information from said memory for configuring said state machine to have the capability of identifying the computer peripheral device to the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standard.

24. A Universal Serial Bus node for a computer peripheral device to be used with the Universal Serial Bus equipped computers using the Universal Serial Bus standard, comprising:

a memory programmable with information related to the Universal Serial Bus and the computer peripheral device;

said memory is a non-volatile memory; and

circuitry connected to said memory responsive to said information for configuring said circuitry to have the capability of providing signals from the computer peripheral device to the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standard.

25. A Universal Serial Bus node for a computer peripheral device to be used with the Universal Serial Bus equipped computers using the Universal Serial Bus standard, comprising:

a memory programmable with information related to the Universal Serial Bus and the computer peripheral device;

said memory is a non-volatile memory;

circuitry connected to said memory responsive to said information for configuring said circuitry to have the capability of providing signals from the computer peripheral device to the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standard; and

said circuitry is a state machine.

26. A Universal Serial Bus node including a computer peripheral device and a Universal Serial Bus equipped computer using the Universal Serial Bus standard, comprising:

said Universal Serial Bus equipped computer queries said computer peripheral device for identification;

a memory programmable with information related to the Universal Serial Bus and the computer peripheral device; and

circuitry connected to said memory responsive to said information for configuring said circuitry to have the capability of providing signals from the computer peripheral device to the Universal Serial Bus equipped computer in conformance with the Universal Serial Bus standard, said circuitry identifies said computer peripheral device to said Universal Serial Bus equipped computer;

said Universal Serial Bus equipped computer responds to said circuitry;

said circuitry responds to said computer peripheral device; and

said computer peripheral device providing signals for said circuitry to provide to said Universal Serial Bus equipped computer, all in conformance with the Universal Serial Bus standard.