Memory controller for controlling memory accesses across networks in distributed shared memory processing systems

• US 6,044,438 A
• Filed: 07/10/1997
• Issued: 03/28/2000
• Est. Priority Date: 07/10/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Olnowich, Howard Thomas
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US08/890,341
• Time in Patent Office: 992 Days
• Field of Search: 711/120, 711/130, 711/141, 711/150, 707/201, 709/213, 709/214, 709/250
• US Class Current: 711/130
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: Y10S 707/99952 Coherency, e.g. same view to multiple users

Abstract

A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.

Claims

1. A memory controller for a local node of a shared memory parallel processing system, said node including a node processor, a node memory, a node cache and an I/O adapter, said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes, said node memory including a changeable portion and an unchangeable portion;

said memory controller comprising;

first means responsive to a request by said processor for access to a memory word for first accessing said node cache of said local node;

second means responsive to said first means being unable to access said memory word in said node cache for accessing said memory word selectively from a cache line in said node memory or remote memory and storing said cache line to said node cache; and

third means responsive to a request by said node processor for writing a memory word to said node cache of said local node by storing immediately said memory word data to the node cache and also to either the node memory or the remote memory.

2. A memory controller for a local node of a shared memory parallel processing system, said node including a node processor, a node memory, a node cache and an I/O adapter, said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes, said node memory including a changeable portion and an unchangeable portion;

said memory controller comprising;

first means responsive to a request by said processor for access to a memory word for first accessing said node cache of said local node;

second means responsive to said first means being unable to access said memory word in said node cache for accessing said memory word selectively from a cache line in said node memory or remote memory and storing said cache line to said node cache;

cache copy update means for sending cache update messages to update corresponding cache lines all remote nodes having copies of a changed cache line; and

cache update message receiving means for replacing a cache line of data with an updated cache line of data received from a remote node.

3. A memory controller for a local node of a shared memory parallel processing system, said node including a node processor, a node memory, a node cache and an I/O adapter, said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes, said node memory including a changeable portion and an unchangeable portion;

said memory controller comprising;

first means responsive to a request by said processor for access to a memory word for first accessing said node cache of said local node;

second means responsive to said first means being unable to access said memory word in said node cache for accessing said memory word selectively from a cache line in said node memory or remote memory and storing said cache line to said node cache; and

remote fetch interrupt means for issuing an interrupt signal to said node processor upon determining that said memory word is located in remote memory for causing said node processor to switch from a first instruction stream thread to a second instruction stream thread.

4. A memory controller for a local node of a shared memory parallel processing system, said node including a node processor, a node memory, a node cache and an I/O adapter, said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes, said node memory including a changeable portion and an unchangeable portion;

said memory controller comprising;

first means responsive to a request by said processor for access to a memory word for first accessing said node cache of said local node;

second means responsive to said first means being unable to access said memory word in said node cache for accessing said memory word selectively from a cache line in said node memory or remote memory and storing said cache line to said node cache; and

data message generation means responsive to a request from a remote node for accessing a cache line identified by a remote request read address for generating a read response message to return the accessed cache line to said remote node, said read response message including a message header comprising

message differentiation indicia for defining said read request message type;

destination node indicia equal to the sector segment of said node memory for said addressed memory word;

source node indicia set to the node ID number of the local node;

message length indicia for defining said read request message as being comprised of said message header only; and

memory address indicia for specifying the memory address of said memory word;

said data message generation means further operable for delivering said read response message to a read send FIFO of said network adapter for transmission to said network and the remote node selected by said destination node indicia.

5. A memory controller for a local node of a shared memory parallel processing system, said node including a node processor, a node memory, a node cache and an I/O adapter, said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes, said node memory including a changeable portion and an unchangeable portion;

said memory controller comprising;

first means responsive to a request by said processor for access to a memory word for first accessing said node cache of said local node;

second means responsive to said first means being unable to access said memory word in said node cache for accessing said memory word selectively from a cache line in said node memory or remote memory and storing said cache line to said node cache;

an invalidation directory; and

cast-out means for deleting a cache line from said node cache when said cache is full to provide space for a new cache line to be stored to said cache; and

for sending the address of the deleted cache line to said invalidation directory to indicate said node no longer has a copy of said cache line.

6. The memory controller of claim 5, further comprising:

cast-out message generation means responsive to said cast-out means deleting a cache line addressed to a remote node for generating a cast-out message to said remote node to send the cast-out address and the local node ID number to said remote node over said network;

cast-out message receiving means for delivering a cast-out address and the source node ID number from the message header of a cast-out message to said invalidation directory.

7. A method for operating memory controller for a local node of a shared memory parallel processing system, said node including a node processor, a node memory, a node cache and an I/O adapter, said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes, said node memory including a changeable portion and an unchangeable portion;

the method comprising the steps of;

responsive to a request by said processor for access to a memory word, accessing said node cache of said local node;

responsive to said first means being unable to access said memory word in said node cache, accessing said memory word selectively from a cache line in said node memory or remote memory and storing said cache line to said node cache; and

responsive to a request by said node processor writing a memory word to said node cache of said local node by storing immediately said memory word data to the node cache and also to either the node memory or the remote memory.

8. A method for operating a memory controller for a local node of a shared memory parallel processing system, said node including a node processor, a node memory, a node cache and an I/O adapter, said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes, said node memory including a changeable portion and an unchangeable portion;

the method comprising the steps of;

responsive to a request by said processor for access to a memory word, accessing said node cache of said local node;

responsive to said first means being unable to access said memory word in said node cache, accessing said memory word selectively from a cache line in said node memory or remote memory and storing said cache line to said node cache; and

issuing an interrupt signal to said node processor upon determining that said memory word is located in remote memory for causing said node processor to switch from a first instruction stream thread to a second instruction stream thread.

9. A memory controller for a local node of a shared memory parallel processing system, said node including a node processor, a node memory, a node cache and an I/O adapter, said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes, said node memory including a changeable portion and an unchangeable portion;

said memory controller comprising;

first means responsive to a request by said node processor for access to a memory word for first accessing said node cache of said local node;

second means responsive to said first means being unable to access said memory word in said node cache for accessing said memory word selectively from a cache line in said node memory or remote memory;

third means for determining whether said memory word requested to be accessed by said processor is located in node memory or remote memory;

fourth means for accessing said memory word from node memory and storing said cache line to said node cache, if said third means determines the requested memory word is located in node memory;

fifth means for generating a read request message over said multi-stage switching network for accessing said memory word from remote memory and storing said cache line to said node cache, if said third means determines the requested memory word is located in remote memory; and

sixth means responsive to a request by said node processor for writing a memory word to said node cache of said local node by storing immediately said memory word data to the node cache and also to either the node memory or the remote memory.

10. A method for operating memory controller for a local node of a shared memory parallel processing system, said node including a node processor, a node memory, a node cache and an I/O adapter, said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes, said node memory including a changeable portion and an unchangeable portion;

the method comprising the steps of;

responding to a request by said node processor for writing a memory word to said node cache of said local node by storing immediately said memory word to the node cache and also to either the node memory or the remote memory;

responding to a request by said processor for access to a memory word by accessing said node cache of said local node;

responding, when said request is unable to access said memory word in said node cache, by accessing said memory word selectively from a cache line in said node memory or remote memory;

determining whether said memory word requested to be accessed by said processor is located in node memory or remote memory;

accessing said memory word from node memory and storing said cache line to said node cache, if said requested memory word is located in node memory; and

generating a read request message over said multi-stage switching network for accessing said memory word from remote memory and storing said cache line to said node cache, if said requested memory word is located in remote memory.

11. A memory controller for a local node of a shared memory parallel processing system, said node including a node processor, a node memory, a node cache and an I/O adapter, said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes, said node memory including a changeable portion and an unchangeable portion;

said memory controller comprising;

first memory control logic responsive to a request by said processor for access to a memory word for first accessing said node cache of said local node;

second memory control logic responsive to said first control logic being unable to access said memory word in said node cache for accessing said memory word selectively from a cache line in said node memory or remote memory and storing said cache line to said node cache; and

third memory control logic responsive to a request by said node processor for writing a memory word to said node cache of said local node by storing immediately said memory word data to the node cache and also to either the node memory or the remote memory.

12. The memory controller of claim 11, further comprising:

remote fetch interrupt logic for issuing an interrupt signal to said node processor upon determining that said memory word is located in remote memory for causing said node processor to switch from a first instruction stream thread to a second instruction stream thread.

13. The memory controller of claim 11, further comprising:

data message generation logic responsive to a request from a remote node for accessing a cache line identified by a remote request read address for generating a read response message to return the accessed cache line to said remote node, said read response message including a message header comprising

message differentiation indicia for defining said read request message type;

destination node indicia equal to the sector segment of said node memory for said addressed memory word;

source node indicia set to the node ID number of the local node;

message length indicia for defining said read request message as being comprised of said message header only; and

memory address indicia for specifying the memory address of said memory word;

said data message generation logic further operable for delivering said read response message to a read send FIFO of said network adapter for transmission to said network and the remote node selected by said destination node indicia.

14. The memory controller of claim 11, further comprising:

an invalidation directory; and

cast-out logic for deleting a cache line from said node cache when said cache is full to provide space for a new cache line to be stored to said cache; and

for sending the address of the deleted cache line to said invalidation directory to indicate said node no longer has a copy of said cache line.

15. The memory controller of claim 14, further comprising:

cast-out message generation logic responsive to said cast-out logic deleting a cache line addressed to a remote node for generating a cast-out message to said remote node to send the cast-out address and the local node ID number to said remote node over said network;

cast-out message receiving logic for delivering a cast-out address and the source node ID number from the message header of a cast-out message to said invalidation directory.

16. The memory controller of claim 11, further comprising:

cache copy update logic for sending cache update messages to update corresponding cache lines all remote nodes having copies of a changed cache line; and

cache update message receiving logic for replacing a cache line of data with an updated cache line of data received from a remote node.