Methods for allocating circuit design portions among physical circuit portions

• US 6,045,252 A
• Filed: 04/22/1998
• Issued: 04/04/2000
• Est. Priority Date: 02/20/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Pedersen, Bruce B.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/064,705
• Time in Patent Office: 713 Days
• Field of Search: 364/488-491, 364/578
• US Class Current: 716/125
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Partitioning of a circuit design to facilitate economical implementation of that circuit in a physical circuit that is made up of two or more physical subcircuits is improved by starting with two different, conventionally produced partitions of the design and combining selected features of those two starting partitions to produce a final partition that is better than either of the starting partitions.

Claims

1. A method of implementing a circuit design in a physical circuit which includes a plurality of physical subcircuits, said circuit design including a plurality of circuit elements and a plurality of connections between said elements, said method comprising:

partitioning said circuit design into a first plurality of design subcircuits;

partitioning said circuit design into a second plurality of design subcircuits, said design subcircuits in said first plurality being different from said design subcircuits in said second plurality; and

selectively combining features from said first and second pluralities of design subcircuits to produce a third plurality of design subcircuits.

2. The method of claim 1 wherein said third plurality of design subcircuits requires fewer of said connections to extend between said design subcircuits in said third plurality than are required to extend between said design subcircuits in either of said first plurality or said second plurality.

3. The method of claim 2 wherein each of said partitionings is performed according to conventional partitioning techniques.

4. The method of claim 3 wherein said first and second pluralities of design subcircuits are each the best of several trials with regard to reducing numbers of said connections that are required to extend between the design subcircuits in the respective first and second pluralities.

5. The method of claim 4 wherein said selectively combining includes coupling selected elements from said first and second pluralities of design subcircuits.

6. A method of implementing a circuit design in a physical circuit which includes a plurality of physical subcircuits, said circuit design including a plurality of circuit elements and a plurality of connections between said elements, said method comprising:

representing said circuit design as a plurality of vertices joined by edges;

partitioning said vertices and edges into a first plurality of design subcircuits;

partitioning said vertices and edges into a second plurality of design subcircuits, said design subcircuits in said first plurality being different from said design subcircuits in said second plurality; and

selectively combining features from said first and second pluralities of design subcircuits to produce a third plurality of design subcircuits which is better than either.

7. The method of claim 6 wherein said third plurality of design subcircuits requires fewer of said connections to extend between said design subcircuits in said third plurality than are required to extend between said design subcircuits in either of said first plurality or said second plurality.

8. The method of claim 7 wherein each of said partitioning is performed according to conventional partitioning techniques.

9. The method of claim 8 wherein each of said first and second pluralities of design subcircuits are the best of several trials with regard to reducing numbers of said connections that are required to extend between the design subcircuits in the respective first and second pluralities.

10. The method of claim 9 wherein said selectively combining includes coupling selected elements from said first and second pluralities of design subcircuits.